Neil Armstrong c987ac6f1f clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL ... On Amlogic Meson GXBB & GXL platforms, the SCPI Cortex-M4 Co-Processor seems to be dependent on the FCLK_DIV2 to be operationnal. The issue occurred since v4.17-rc1 by freezing the kernel boot when the 'schedutil' cpufreq governor was selected as default : [ 12.071837] scpi_protocol scpi: SCP Protocol 0.0 Firmware 0.0.0 version domain-0 init dvfs: 4 [ 12.087757] hctosys: unable to open rtc device (rtc0) [ 12.087907] cfg80211: Loading compiled-in X.509 certificates for regulatory database [ 12.102241] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' But when disabling the MMC driver, the boot finished but cpufreq failed to change the CPU frequency : [ 12.153045] cpufreq: __target_index: Failed to change cpu frequency: -5 A bisect between v4.16 and v4.16-rc1 gave 05f814402d ("clk: meson: add fdiv clock gates") to be the first bad commit. This commit added support for the missing clock gates before the fixed PLL fixed dividers (FCLK_DIVx) and the clock framework basically disabled all the unused fixed dividers, thus disabled a critical clock path for the SCPI Co-Processor. This patch simply sets the FCLK_DIV2 gate as critical to ensure nobody can disable it. Fixes: 05f814402d ("clk: meson: add fdiv clock gates") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> [few corrections in the commit description] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>		2018-06-19 17:20:11 +02:00
..
axg-aoclk.c	clk: meson-axg: Add AO Clock and Reset controller driver	2018-05-15 14:19:43 +02:00
axg-aoclk.h	clk: meson-axg: Add AO Clock and Reset controller driver	2018-05-15 14:19:43 +02:00
axg.c	clk: meson: axg: let mpll clocks round closest	2018-05-21 11:31:59 +02:00
axg.h	clk: meson: add fdiv clock gates	2018-03-13 10:09:58 +01:00
clk-audio-divider.c	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
clk-mpll.c	clk: meson: mpll: add round closest support	2018-05-21 11:31:29 +02:00
clk-pll.c	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
clk-regmap.c	This time we have a good set of changes to the core framework that do some	2018-06-09 12:06:24 -07:00
clk-regmap.h	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
clkc.h	clk: meson: mpll: add round closest support	2018-05-21 11:31:29 +02:00
gxbb-aoclk-32k.c	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
gxbb-aoclk.c	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
gxbb-aoclk.h	This time we have a good set of changes to the core framework that do some	2018-06-09 12:06:24 -07:00
gxbb.c	clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL	2018-06-19 17:20:11 +02:00
gxbb.h	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
Kconfig	clk: meson-axg: Add AO Clock and Reset controller driver	2018-05-15 14:19:43 +02:00
Makefile	clk: meson-axg: Add AO Clock and Reset controller driver	2018-05-15 14:19:43 +02:00
meson-aoclk.c	clk: meson: aoclk: refactor common code into dedicated file	2018-05-15 14:19:42 +02:00
meson-aoclk.h	clk: meson: aoclk: refactor common code into dedicated file	2018-05-15 14:19:42 +02:00
meson8b.c	This time we have a good set of changes to the core framework that do some	2018-06-09 12:06:24 -07:00
meson8b.h	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00