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80e87442e6
The enetc MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. This driver is shared with the Felix DSA switch, so update that at the same time. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
67 lines
2 KiB
C
67 lines
2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2019 NXP */
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#ifndef _FSL_ENETC_MDIO_H_
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#define _FSL_ENETC_MDIO_H_
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#include <linux/phy.h>
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/* PCS registers */
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#define ENETC_PCS_LINK_TIMER1 0x12
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#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
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#define ENETC_PCS_LINK_TIMER2 0x13
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#define ENETC_PCS_LINK_TIMER2_VAL 0x0003
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#define ENETC_PCS_IF_MODE 0x14
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#define ENETC_PCS_IF_MODE_SGMII_EN BIT(0)
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#define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1)
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#define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2))
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#define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3)
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/* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset
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* Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS
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* still thinks it's at gigabit.
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*/
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enum enetc_pcs_speed {
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ENETC_PCS_SPEED_10 = 0,
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ENETC_PCS_SPEED_100 = 1,
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ENETC_PCS_SPEED_1000 = 2,
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ENETC_PCS_SPEED_2500 = 2,
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};
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struct enetc_hw;
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struct enetc_mdio_priv {
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struct enetc_hw *hw;
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int mdio_base;
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};
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#if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO)
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int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum);
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int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum,
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u16 value);
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int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, int devad, int regnum);
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int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, int devad, int regnum,
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u16 value);
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struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs);
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#else
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static inline int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id,
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int regnum)
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{ return -EINVAL; }
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static inline int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id,
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int regnum, u16 value)
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{ return -EINVAL; }
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static inline int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id,
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int devad, int regnum)
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{ return -EINVAL; }
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static inline int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id,
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int devad, int regnum, u16 value)
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{ return -EINVAL; }
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struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs)
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{ return ERR_PTR(-EINVAL); }
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#endif
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#endif
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