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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-20 01:20:54 +00:00
1f640552d9
Thumb2 uses R7 rather than R11 as the frame pointer, and even if we rarely use a frame pointer to begin with when building in Thumb2 mode, there are cases where it is required by the compiler (Clang when inserting profiling hooks via -pg) However, preserving and restoring the frame pointer is risky, as any unhandled exceptions raised in the mean time will produce a bogus backtrace, and it would be better not to touch the frame pointer at all. This is the case even when CONFIG_FRAME_POINTER is not set, as the unwind directive used by the unwinder may also use R7 or R11 as the unwind anchor, even if the frame pointer is not managed strictly according to the frame pointer ABI. So let's tweak the cacheflush asm code not to clobber R7 or R11 at all, so that we can drop R7 from the clobber lists of the inline asm blocks that call these routines, and remove the code that preserves/restores R11. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
480 lines
13 KiB
ArmAsm
480 lines
13 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/mm/cache-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2005 ARM Ltd.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/errno.h>
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#include <asm/unwind.h>
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#include <asm/hardware/cache-b15-rac.h>
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#include "proc-macros.S"
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#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
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.globl icache_size
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.data
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.align 2
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icache_size:
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.long 64
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.text
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#endif
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/*
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*
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* This function needs to be called for both secondary cores startup and
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* primary core resume procedures.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
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isb
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mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
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movw r3, #0x3ff
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and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3]
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clz r1, r3 @ WayShift
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mov r2, #1
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mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
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movs r1, r2, lsl r1 @ #1 shifted left by same amount
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moveq r1, #1 @ r1 needs value > 0 even if only 1 way
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and r2, r0, #0x7
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add r2, r2, #4 @ SetShift
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1: movw ip, #0x7fff
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and r0, ip, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13]
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2: mov ip, r0, lsl r2 @ NumSet << SetShift
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orr ip, ip, r3 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, ip, c7, c6, 2
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subs r0, r0, #1 @ Set--
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bpl 2b
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subs r3, r3, r1 @ Way--
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bcc 3f
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mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
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b 1b
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3: dsb st
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isb
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ret lr
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ENDPROC(v7_invalidate_l1)
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/*
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* v7_flush_icache_all()
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*
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* Flush the whole I-cache.
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*
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* Registers:
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* r0 - set to 0
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*/
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ENTRY(v7_flush_icache_all)
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mov r0, #0
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ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
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ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
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ret lr
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ENDPROC(v7_flush_icache_all)
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/*
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* v7_flush_dcache_louis()
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*
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* Flush the D-cache up to the Level of Unification Inner Shareable
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*
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* Corrupted registers: r0-r6, r9-r10
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*/
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ENTRY(v7_flush_dcache_louis)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
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ALT_SMP(mov r3, r0, lsr #20) @ move LoUIS into position
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ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position
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ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
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bne start_flush_levels @ LoU != 0, start flushing
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#ifdef CONFIG_ARM_ERRATA_643719
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ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
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ALT_UP( ret lr) @ LoUU is zero, so nothing to do
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movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
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movt r1, #:upper16:(0x410fc090 >> 4)
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teq r1, r2, lsr #4 @ test for errata affected core and if so...
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moveq r3, #1 << 1 @ fix LoUIS value
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beq start_flush_levels @ start flushing cache levels
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#endif
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ret lr
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ENDPROC(v7_flush_dcache_louis)
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r6, r9-r10
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v7_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq finished @ if loc is 0, then no need to clean
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start_flush_levels:
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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#ifdef CONFIG_PREEMPTION
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save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
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#endif
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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#ifdef CONFIG_PREEMPTION
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restore_irqs_notrace r9
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#endif
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r6, #0x7fff
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and r1, r6, r1, lsr #13 @ extract max number of the index size
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mov r6, #1
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movne r4, r4, lsl r5 @ # of ways shifted into bits [31:...]
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movne r6, r6, lsl r5 @ 1 shifted left by same amount
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loop1:
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mov r9, r1 @ create working copy of max index
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loop2:
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mov r5, r9, lsl r2 @ factor set number into r5
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orr r5, r5, r4 @ factor way number into r5
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orr r5, r5, r10 @ factor cache level into r5
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mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, r6 @ decrement the way
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bcs loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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#ifdef CONFIG_ARM_ERRATA_814220
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dsb
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#endif
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bgt flush_levels
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finished:
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mov r10, #0 @ switch back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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ret lr
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ENDPROC(v7_flush_dcache_all)
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/*
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* v7_flush_cache_all()
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*
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* Flush the entire cache system.
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* The data cache flush is now achieved using atomic clean / invalidates
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* working outwards from L1 cache. This is done using Set/Way based cache
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* maintenance instructions.
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* The instruction cache can still be invalidated back to the point of
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* unification in a single instruction.
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*
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*/
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ENTRY(v7_flush_kern_cache_all)
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stmfd sp!, {r4-r6, r9-r10, lr}
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bl v7_flush_dcache_all
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mov r0, #0
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ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
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ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
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ldmfd sp!, {r4-r6, r9-r10, lr}
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ret lr
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ENDPROC(v7_flush_kern_cache_all)
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/*
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* v7_flush_kern_cache_louis(void)
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*
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* Flush the data cache up to Level of Unification Inner Shareable.
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* Invalidate the I-cache to the point of unification.
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*/
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ENTRY(v7_flush_kern_cache_louis)
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stmfd sp!, {r4-r6, r9-r10, lr}
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bl v7_flush_dcache_louis
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mov r0, #0
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ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
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ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
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ldmfd sp!, {r4-r6, r9-r10, lr}
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ret lr
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ENDPROC(v7_flush_kern_cache_louis)
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/*
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* v7_flush_cache_all()
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*
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* Flush all TLB entries in a particular address space
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v7_flush_user_cache_all)
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/*FALLTHROUGH*/
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/*
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* v7_flush_cache_range(start, end, flags)
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*
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* Flush a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vm_area_struct flags describing address space
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*
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* It is assumed that:
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* - we have a VIPT cache.
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*/
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ENTRY(v7_flush_user_cache_range)
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ret lr
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ENDPROC(v7_flush_user_cache_all)
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ENDPROC(v7_flush_user_cache_range)
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/*
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* v7_coherent_kern_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v7_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* v7_coherent_user_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v7_coherent_user_range)
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UNWIND(.fnstart )
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r12, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
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add r12, r12, r2
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cmp r12, r1
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blo 1b
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dsb ishst
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#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
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ldr r3, =icache_size
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ldr r2, [r3, #0]
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#else
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icache_line_size r2, r3
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#endif
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sub r3, r2, #1
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bic r12, r0, r3
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2:
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USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
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add r12, r12, r2
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cmp r12, r1
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blo 2b
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mov r0, #0
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ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
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ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
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dsb ishst
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isb
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ret lr
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/*
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* Fault handling for the cache operation above. If the virtual address in r0
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* isn't mapped, fail with -EFAULT.
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*/
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9001:
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#ifdef CONFIG_ARM_ERRATA_775420
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dsb
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#endif
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mov r0, #-EFAULT
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ret lr
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UNWIND(.fnend )
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ENDPROC(v7_coherent_kern_range)
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ENDPROC(v7_coherent_user_range)
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/*
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* v7_flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure that the data held in the page kaddr is written back
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* to the page in question.
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(v7_flush_kern_dcache_area)
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dcache_line_size r2, r3
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add r1, r0, r1
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sub r3, r2, #1
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7_flush_kern_dcache_area)
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/*
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* v7_dma_inv_range(start,end)
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*
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* Invalidate the data cache within the specified region; we will
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* be performing a DMA operation in this region and we want to
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* purge old data in the cache.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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v7_dma_inv_range:
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dcache_line_size r2, r3
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sub r3, r2, #1
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tst r0, r3
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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addne r0, r0, r2
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tst r1, r3
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bic r1, r1, r3
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mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
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cmp r0, r1
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1:
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mcrlo p15, 0, r0, c7, c6, 1 @ invalidate D / U line
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addlo r0, r0, r2
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cmplo r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7_dma_inv_range)
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/*
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* v7_dma_clean_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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v7_dma_clean_range:
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7_dma_clean_range)
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/*
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* v7_dma_flush_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v7_dma_flush_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7_dma_flush_range)
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v7_dma_map_area)
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add r1, r1, r0
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teq r2, #DMA_FROM_DEVICE
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beq v7_dma_inv_range
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b v7_dma_clean_range
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ENDPROC(v7_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v7_dma_unmap_area)
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add r1, r1, r0
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teq r2, #DMA_TO_DEVICE
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bne v7_dma_inv_range
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ret lr
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ENDPROC(v7_dma_unmap_area)
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions v7
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/* The Broadcom Brahma-B15 read-ahead cache requires some modifications
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* to the v7_cache_fns, we only override the ones we need
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*/
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#ifndef CONFIG_CACHE_B15_RAC
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globl_equ b15_flush_kern_cache_all, v7_flush_kern_cache_all
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#endif
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globl_equ b15_flush_icache_all, v7_flush_icache_all
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globl_equ b15_flush_kern_cache_louis, v7_flush_kern_cache_louis
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globl_equ b15_flush_user_cache_all, v7_flush_user_cache_all
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globl_equ b15_flush_user_cache_range, v7_flush_user_cache_range
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globl_equ b15_coherent_kern_range, v7_coherent_kern_range
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globl_equ b15_coherent_user_range, v7_coherent_user_range
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globl_equ b15_flush_kern_dcache_area, v7_flush_kern_dcache_area
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globl_equ b15_dma_map_area, v7_dma_map_area
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globl_equ b15_dma_unmap_area, v7_dma_unmap_area
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globl_equ b15_dma_flush_range, v7_dma_flush_range
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define_cache_functions b15
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