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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
310 lines
7.4 KiB
C
310 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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*
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* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2011 Wind River Systems,
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* written by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/memblock.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/of_address.h>
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#include <asm/cpu-info.h>
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/*
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* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
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* assignments.
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*/
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/*
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* The PCI controller list.
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*/
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static LIST_HEAD(controllers);
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static int pci_initialized;
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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resource_size_t
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pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_controller *hose = dev->sysdata;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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/* Make sure we start at our min on all hoses */
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if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
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start = PCIBIOS_MIN_IO + hose->io_resource->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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} else if (res->flags & IORESOURCE_MEM) {
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/* Make sure we start at our min on all hoses */
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if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
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start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
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}
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return start;
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}
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static void pcibios_scanbus(struct pci_controller *hose)
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{
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static int next_busno;
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static int need_domain_info;
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LIST_HEAD(resources);
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struct pci_bus *bus;
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struct pci_host_bridge *bridge;
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int ret;
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bridge = pci_alloc_host_bridge(0);
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if (!bridge)
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return;
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if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
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next_busno = (*hose->get_busno)();
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pci_add_resource_offset(&resources,
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hose->mem_resource, hose->mem_offset);
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pci_add_resource_offset(&resources,
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hose->io_resource, hose->io_offset);
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pci_add_resource(&resources, hose->busn_resource);
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list_splice_init(&resources, &bridge->windows);
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bridge->dev.parent = NULL;
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bridge->sysdata = hose;
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bridge->busnr = next_busno;
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bridge->ops = hose->pci_ops;
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bridge->swizzle_irq = pci_common_swizzle;
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bridge->map_irq = pcibios_map_irq;
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret) {
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pci_free_host_bridge(bridge);
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return;
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}
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hose->bus = bus = bridge->bus;
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need_domain_info = need_domain_info || pci_domain_nr(bus);
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set_pci_need_domain_info(hose, need_domain_info);
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next_busno = bus->busn_res.end + 1;
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/* Don't allow 8-bit bus number overflow inside the hose -
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reserve some space for bridges. */
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if (next_busno > 224) {
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next_busno = 0;
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need_domain_info = 1;
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}
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/*
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* We insert PCI resources into the iomem_resource and
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* ioport_resource trees in either pci_bus_claim_resources()
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* or pci_bus_assign_resources().
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*/
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if (pci_has_flag(PCI_PROBE_ONLY)) {
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pci_bus_claim_resources(bus);
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} else {
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struct pci_bus *child;
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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}
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pci_bus_add_devices(bus);
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}
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#ifdef CONFIG_OF
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void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
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{
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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pr_info("PCI host bridge %pOF ranges:\n", node);
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hose->of_node = node;
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if (of_pci_range_parser_init(&parser, node))
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return;
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for_each_of_pci_range(&parser, &range) {
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struct resource *res = NULL;
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switch (range.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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pr_info(" IO 0x%016llx..0x%016llx\n",
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range.cpu_addr,
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range.cpu_addr + range.size - 1);
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hose->io_map_base =
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(unsigned long)ioremap(range.cpu_addr,
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range.size);
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res = hose->io_resource;
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break;
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case IORESOURCE_MEM:
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pr_info(" MEM 0x%016llx..0x%016llx\n",
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range.cpu_addr,
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range.cpu_addr + range.size - 1);
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res = hose->mem_resource;
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break;
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}
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if (res != NULL)
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of_pci_range_to_resource(&range, node, res);
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}
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}
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struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return of_node_get(hose->of_node);
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}
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#endif
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static DEFINE_MUTEX(pci_scan_mutex);
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void register_pci_controller(struct pci_controller *hose)
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{
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struct resource *parent;
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parent = hose->mem_resource->parent;
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if (!parent)
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parent = &iomem_resource;
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if (request_resource(parent, hose->mem_resource) < 0)
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goto out;
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parent = hose->io_resource->parent;
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if (!parent)
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parent = &ioport_resource;
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if (request_resource(parent, hose->io_resource) < 0) {
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release_resource(hose->mem_resource);
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goto out;
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}
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INIT_LIST_HEAD(&hose->list);
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list_add_tail(&hose->list, &controllers);
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/*
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* Do not panic here but later - this might happen before console init.
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*/
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if (!hose->io_map_base) {
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printk(KERN_WARNING
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"registering PCI controller with io_map_base unset\n");
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}
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/*
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* Scan the bus if it is register after the PCI subsystem
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* initialization.
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*/
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if (pci_initialized) {
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mutex_lock(&pci_scan_mutex);
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pcibios_scanbus(hose);
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mutex_unlock(&pci_scan_mutex);
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}
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return;
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out:
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printk(KERN_WARNING
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"Skipping PCI bus scan due to resource conflict\n");
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose;
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/* Scan all of the recorded PCI controllers. */
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list_for_each_entry(hose, &controllers, list)
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pcibios_scanbus(hose);
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pci_initialized = 1;
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return 0;
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}
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subsys_initcall(pcibios_init);
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static int pcibios_enable_resources(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1<<idx)))
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continue;
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r = &dev->resource[idx];
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if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
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continue;
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if ((idx == PCI_ROM_RESOURCE) &&
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(!(r->flags & IORESOURCE_ROM_ENABLE)))
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continue;
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if (!r->start && r->end) {
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pci_err(dev,
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"can't enable device: resource collisions\n");
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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int err;
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if ((err = pcibios_enable_resources(dev, mask)) < 0)
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return err;
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return pcibios_plat_dev_init(dev);
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}
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_read_bridge_bases(bus);
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}
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}
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char * (*pcibios_plat_setup)(char *str) __initdata;
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char *__init pcibios_setup(char *str)
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{
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if (pcibios_plat_setup)
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return pcibios_plat_setup(str);
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return str;
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}
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