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Based on 1 normalized pattern(s): this program is free software you can distribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 32 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.531157061@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
242 lines
7.3 KiB
C
242 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* MIPS boards specific PCI support.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/gt64120.h>
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#include <asm/mips-cps.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/bonito64.h>
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#include <asm/mips-boards/msc01_pci.h>
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static struct resource bonito64_mem_resource = {
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.name = "Bonito PCI MEM",
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.flags = IORESOURCE_MEM,
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};
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static struct resource bonito64_io_resource = {
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.name = "Bonito PCI I/O",
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.start = 0x00000000UL,
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.end = 0x000fffffUL,
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.flags = IORESOURCE_IO,
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};
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static struct resource gt64120_mem_resource = {
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.name = "GT-64120 PCI MEM",
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.flags = IORESOURCE_MEM,
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};
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static struct resource gt64120_io_resource = {
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.name = "GT-64120 PCI I/O",
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.flags = IORESOURCE_IO,
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};
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static struct resource msc_mem_resource = {
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.name = "MSC PCI MEM",
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.flags = IORESOURCE_MEM,
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};
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static struct resource msc_io_resource = {
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.name = "MSC PCI I/O",
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.flags = IORESOURCE_IO,
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};
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extern struct pci_ops bonito64_pci_ops;
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extern struct pci_ops gt64xxx_pci0_ops;
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extern struct pci_ops msc_pci_ops;
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static struct pci_controller bonito64_controller = {
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.pci_ops = &bonito64_pci_ops,
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.io_resource = &bonito64_io_resource,
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.mem_resource = &bonito64_mem_resource,
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.io_offset = 0x00000000UL,
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};
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static struct pci_controller gt64120_controller = {
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.pci_ops = >64xxx_pci0_ops,
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.io_resource = >64120_io_resource,
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.mem_resource = >64120_mem_resource,
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};
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static struct pci_controller msc_controller = {
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.pci_ops = &msc_pci_ops,
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.io_resource = &msc_io_resource,
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.mem_resource = &msc_mem_resource,
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};
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void __init mips_pcibios_init(void)
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{
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struct pci_controller *controller;
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resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_GT64120:
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/*
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* Due to a bug in the Galileo system controller, we need
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* to setup the PCI BAR for the Galileo internal registers.
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* This should be done in the bios/bootprom and will be
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* fixed in a later revision of YAMON (the MIPS boards
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* boot prom).
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*/
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
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(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
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((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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/* Perform the write */
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GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
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/* Set up resource ranges from the controller's registers. */
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start = GT_READ(GT_PCI0M0LD_OFS);
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end = GT_READ(GT_PCI0M0HD_OFS);
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map = GT_READ(GT_PCI0M0REMAP_OFS);
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end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
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start1 = GT_READ(GT_PCI0M1LD_OFS);
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end1 = GT_READ(GT_PCI0M1HD_OFS);
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map1 = GT_READ(GT_PCI0M1REMAP_OFS);
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end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
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/* Cannot support multiple windows, use the wider. */
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if (end1 - start1 > end - start) {
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start = start1;
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end = end1;
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map = map1;
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}
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mask = ~(start ^ end);
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/* We don't support remapping with a discontiguous mask. */
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BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
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mask != ~((mask & -mask) - 1));
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gt64120_mem_resource.start = start;
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gt64120_mem_resource.end = end;
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gt64120_controller.mem_offset = (start & mask) - (map & mask);
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/* Addresses are 36-bit, so do shifts in the destinations. */
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gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
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gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
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gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
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gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
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start = GT_READ(GT_PCI0IOLD_OFS);
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end = GT_READ(GT_PCI0IOHD_OFS);
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map = GT_READ(GT_PCI0IOREMAP_OFS);
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end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
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mask = ~(start ^ end);
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/* We don't support remapping with a discontiguous mask. */
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BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
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mask != ~((mask & -mask) - 1));
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gt64120_io_resource.start = map & mask;
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gt64120_io_resource.end = (map & mask) | ~mask;
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gt64120_controller.io_offset = 0;
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/* Addresses are 36-bit, so do shifts in the destinations. */
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gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
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gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
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gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
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controller = >64120_controller;
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break;
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case MIPS_REVISION_SCON_BONITO:
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/* Set up resource ranges from the controller's registers. */
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map = BONITO_PCIMAP;
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map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
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BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
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map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
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BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
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map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
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BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
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/* Combine as many adjacent windows as possible. */
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map = map1;
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start = BONITO_PCILO0_BASE;
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end = 1;
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if (map3 == map2 + 1) {
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map = map2;
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start = BONITO_PCILO1_BASE;
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end++;
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}
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if (map2 == map1 + 1) {
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map = map1;
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start = BONITO_PCILO0_BASE;
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end++;
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}
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bonito64_mem_resource.start = start;
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bonito64_mem_resource.end = start +
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BONITO_PCIMAP_WINBASE(end) - 1;
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bonito64_controller.mem_offset = start -
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BONITO_PCIMAP_WINBASE(map);
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controller = &bonito64_controller;
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break;
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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/* Set up resource ranges from the controller's registers. */
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MSC_READ(MSC01_PCI_SC2PMBASL, start);
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MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
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MSC_READ(MSC01_PCI_SC2PMMAPL, map);
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msc_mem_resource.start = start & mask;
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msc_mem_resource.end = (start & mask) | ~mask;
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msc_controller.mem_offset = (start & mask) - (map & mask);
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if (mips_cps_numiocu(0)) {
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write_gcr_reg0_base(start);
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write_gcr_reg0_mask(mask |
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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}
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MSC_READ(MSC01_PCI_SC2PIOBASL, start);
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MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
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MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
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msc_io_resource.start = map & mask;
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msc_io_resource.end = (map & mask) | ~mask;
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msc_controller.io_offset = 0;
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ioport_resource.end = ~mask;
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if (mips_cps_numiocu(0)) {
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write_gcr_reg1_base(start);
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write_gcr_reg1_mask(mask |
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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}
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/* If ranges overlap I/O takes precedence. */
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start = start & mask;
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end = start | ~mask;
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if ((start >= msc_mem_resource.start &&
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start <= msc_mem_resource.end) ||
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(end >= msc_mem_resource.start &&
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end <= msc_mem_resource.end)) {
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/* Use the larger space. */
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start = max(start, msc_mem_resource.start);
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end = min(end, msc_mem_resource.end);
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if (start - msc_mem_resource.start >=
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msc_mem_resource.end - end)
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msc_mem_resource.end = start - 1;
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else
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msc_mem_resource.start = end + 1;
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}
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controller = &msc_controller;
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break;
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default:
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return;
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}
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/* PIIX4 ACPI starts at 0x1000 */
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if (controller->io_resource->start < 0x00001000UL)
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controller->io_resource->start = 0x00001000UL;
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iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
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ioport_resource.end = controller->io_resource->end;
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controller->io_map_base = mips_io_port_base;
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register_pci_controller(controller);
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}
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