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![Lorenzo Pieralisi](/assets/img/avatar_default.png)
The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Current DT and ACPI host bridge controllers map PCI configuration space (ECAM and ECAM-derivative) into the virtual address space through ioremap() calls, that are non-cacheable device accesses on most architectures, but may provide "bufferable" or "posted" write semantics in architecture like eg ARM/ARM64 that allow ioremap'ed regions writes to be buffered in the bus connecting the host CPU to the PCI fabric; this behaviour, as underlined in the PCIe specifications, may trigger transactions ordering rules and must be prevented. Introduce a new generic and explicit API to create a memory mapping for ECAM and ECAM-derivative config space area that defaults to ioremap_nocache() (which should provide a sane default behaviour) but still allowing architectures on which ioremap_nocache() results in posted write transactions to override the function call with an arch specific implementation that complies with the PCI specifications for configuration transactions. [bhelgaas: fold in #ifdef CONFIG_PCI wrapper] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com>
187 lines
5.7 KiB
C
187 lines
5.7 KiB
C
/*
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* Copyright 2006 PathScale, Inc. All Rights Reserved.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef _LINUX_IO_H
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#define _LINUX_IO_H
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include <asm/page.h>
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struct device;
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struct resource;
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__visible void __iowrite32_copy(void __iomem *to, const void *from, size_t count);
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void __ioread32_copy(void *to, const void __iomem *from, size_t count);
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void __iowrite64_copy(void __iomem *to, const void *from, size_t count);
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#ifdef CONFIG_MMU
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int ioremap_page_range(unsigned long addr, unsigned long end,
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phys_addr_t phys_addr, pgprot_t prot);
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#else
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static inline int ioremap_page_range(unsigned long addr, unsigned long end,
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phys_addr_t phys_addr, pgprot_t prot)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
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void __init ioremap_huge_init(void);
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int arch_ioremap_pud_supported(void);
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int arch_ioremap_pmd_supported(void);
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#else
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static inline void ioremap_huge_init(void) { }
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#endif
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/*
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* Managed iomap interface
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*/
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#ifdef CONFIG_HAS_IOPORT_MAP
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void __iomem * devm_ioport_map(struct device *dev, unsigned long port,
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unsigned int nr);
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void devm_ioport_unmap(struct device *dev, void __iomem *addr);
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#else
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static inline void __iomem *devm_ioport_map(struct device *dev,
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unsigned long port,
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unsigned int nr)
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{
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return NULL;
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}
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static inline void devm_ioport_unmap(struct device *dev, void __iomem *addr)
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{
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}
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#endif
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#define IOMEM_ERR_PTR(err) (__force void __iomem *)ERR_PTR(err)
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void __iomem *devm_ioremap(struct device *dev, resource_size_t offset,
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resource_size_t size);
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void __iomem *devm_ioremap_nocache(struct device *dev, resource_size_t offset,
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resource_size_t size);
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void __iomem *devm_ioremap_wc(struct device *dev, resource_size_t offset,
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resource_size_t size);
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void devm_iounmap(struct device *dev, void __iomem *addr);
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int check_signature(const volatile void __iomem *io_addr,
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const unsigned char *signature, int length);
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void devm_ioremap_release(struct device *dev, void *res);
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void *devm_memremap(struct device *dev, resource_size_t offset,
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size_t size, unsigned long flags);
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void devm_memunmap(struct device *dev, void *addr);
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void *__devm_memremap_pages(struct device *dev, struct resource *res);
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#ifdef CONFIG_PCI
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/*
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* The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and
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* Posting") mandate non-posted configuration transactions. There is
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* no ioremap API in the kernel that can guarantee non-posted write
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* semantics across arches so provide a default implementation for
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* mapping PCI config space that defaults to ioremap_nocache(); arches
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* should override it if they have memory mapping implementations that
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* guarantee non-posted writes semantics to make the memory mapping
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* compliant with the PCI specification.
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*/
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#ifndef pci_remap_cfgspace
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#define pci_remap_cfgspace pci_remap_cfgspace
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static inline void __iomem *pci_remap_cfgspace(phys_addr_t offset,
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size_t size)
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{
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return ioremap_nocache(offset, size);
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}
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#endif
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#endif
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/*
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* Some systems do not have legacy ISA devices.
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* /dev/port is not a valid interface on these systems.
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* So for those archs, <asm/io.h> should define the following symbol.
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*/
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#ifndef arch_has_dev_port
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#define arch_has_dev_port() (1)
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#endif
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/*
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* Some systems (x86 without PAT) have a somewhat reliable way to mark a
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* physical address range such that uncached mappings will actually
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* end up write-combining. This facility should be used in conjunction
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* with pgprot_writecombine, ioremap-wc, or set_memory_wc, since it has
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* no effect if the per-page mechanisms are functional.
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* (On x86 without PAT, these functions manipulate MTRRs.)
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*
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* arch_phys_del_wc(0) or arch_phys_del_wc(any error code) is guaranteed
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* to have no effect.
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*/
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#ifndef arch_phys_wc_add
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static inline int __must_check arch_phys_wc_add(unsigned long base,
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unsigned long size)
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{
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return 0; /* It worked (i.e. did nothing). */
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}
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static inline void arch_phys_wc_del(int handle)
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{
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}
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#define arch_phys_wc_add arch_phys_wc_add
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#ifndef arch_phys_wc_index
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static inline int arch_phys_wc_index(int handle)
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{
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return -1;
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}
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#define arch_phys_wc_index arch_phys_wc_index
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#endif
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#endif
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enum {
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/* See memremap() kernel-doc for usage description... */
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MEMREMAP_WB = 1 << 0,
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MEMREMAP_WT = 1 << 1,
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MEMREMAP_WC = 1 << 2,
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};
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void *memremap(resource_size_t offset, size_t size, unsigned long flags);
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void memunmap(void *addr);
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/*
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* On x86 PAT systems we have memory tracking that keeps track of
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* the allowed mappings on memory ranges. This tracking works for
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* all the in-kernel mapping APIs (ioremap*), but where the user
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* wishes to map a range from a physical device into user memory
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* the tracking won't be updated. This API is to be used by
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* drivers which remap physical device pages into userspace,
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* and wants to make sure they are mapped WC and not UC.
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*/
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#ifndef arch_io_reserve_memtype_wc
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static inline int arch_io_reserve_memtype_wc(resource_size_t base,
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resource_size_t size)
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{
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return 0;
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}
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static inline void arch_io_free_memtype_wc(resource_size_t base,
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resource_size_t size)
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{
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}
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#endif
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#endif /* _LINUX_IO_H */
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