789 lines
22 KiB
C
789 lines
22 KiB
C
/*
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* Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MLX5_EN_H__
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#define __MLX5_EN_H__
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#include <linux/if_vlan.h>
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#include <linux/etherdevice.h>
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/qp.h>
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#include <linux/mlx5/cq.h>
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#include <linux/mlx5/port.h>
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#include <linux/mlx5/vport.h>
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#include <linux/mlx5/transobj.h>
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#include <linux/rhashtable.h>
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#include "wq.h"
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#include "mlx5_core.h"
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#include "en_stats.h"
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#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
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#define MLX5E_MAX_NUM_TC 8
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#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
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#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
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#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
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#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
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#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
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#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
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#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
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#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
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#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
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#define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
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#define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
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#define MLX5_MPWRQ_LOG_WQE_SZ 17
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#define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
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MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
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#define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
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#define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
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MLX5_MPWRQ_WQE_PAGE_ORDER)
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#define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
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BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
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#define MLX5_UMR_ALIGN (2048)
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#define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
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#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
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#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
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#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
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#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
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#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
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#define MLX5E_LOG_INDIR_RQT_SIZE 0x7
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#define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
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#define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
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#define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
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#define MLX5E_TX_CQ_POLL_BUDGET 128
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#define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
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#define MLX5E_SQ_BF_BUDGET 16
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#define MLX5E_NUM_MAIN_GROUPS 9
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static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
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{
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switch (wq_type) {
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case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
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return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
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wq_size / 2);
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default:
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return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
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wq_size / 2);
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}
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}
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static inline int mlx5_min_log_rq_size(int wq_type)
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{
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switch (wq_type) {
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case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
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return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
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default:
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return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
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}
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}
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static inline int mlx5_max_log_rq_size(int wq_type)
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{
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switch (wq_type) {
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case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
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return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
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default:
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return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
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}
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}
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struct mlx5e_tx_wqe {
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struct mlx5_wqe_ctrl_seg ctrl;
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struct mlx5_wqe_eth_seg eth;
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};
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struct mlx5e_rx_wqe {
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struct mlx5_wqe_srq_next_seg next;
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struct mlx5_wqe_data_seg data;
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};
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struct mlx5e_umr_wqe {
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struct mlx5_wqe_ctrl_seg ctrl;
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struct mlx5_wqe_umr_ctrl_seg uctrl;
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struct mlx5_mkey_seg mkc;
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struct mlx5_wqe_data_seg data;
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};
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static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
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"rx_cqe_moder",
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};
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enum mlx5e_priv_flag {
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MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
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};
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#define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \
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do { \
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if (enable) \
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priv->pflags |= pflag; \
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else \
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priv->pflags &= ~pflag; \
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} while (0)
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#ifdef CONFIG_MLX5_CORE_EN_DCB
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#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
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#define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
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#endif
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struct mlx5e_cq_moder {
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u16 usec;
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u16 pkts;
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};
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struct mlx5e_params {
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u8 log_sq_size;
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u8 rq_wq_type;
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u8 mpwqe_log_stride_sz;
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u8 mpwqe_log_num_strides;
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u8 log_rq_size;
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u16 num_channels;
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u8 num_tc;
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u8 rx_cq_period_mode;
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bool rx_cqe_compress_admin;
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bool rx_cqe_compress;
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struct mlx5e_cq_moder rx_cq_moderation;
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struct mlx5e_cq_moder tx_cq_moderation;
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u16 min_rx_wqes;
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bool lro_en;
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u32 lro_wqe_sz;
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u16 tx_max_inline;
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u8 rss_hfunc;
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u8 toeplitz_hash_key[40];
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u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
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bool vlan_strip_disable;
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#ifdef CONFIG_MLX5_CORE_EN_DCB
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struct ieee_ets ets;
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#endif
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bool rx_am_enabled;
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};
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struct mlx5e_tstamp {
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rwlock_t lock;
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struct cyclecounter cycles;
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struct timecounter clock;
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struct hwtstamp_config hwtstamp_config;
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u32 nominal_c_mult;
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unsigned long overflow_period;
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struct delayed_work overflow_work;
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struct mlx5_core_dev *mdev;
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struct ptp_clock *ptp;
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struct ptp_clock_info ptp_info;
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};
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enum {
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MLX5E_RQ_STATE_POST_WQES_ENABLE,
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MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
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MLX5E_RQ_STATE_AM,
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};
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struct mlx5e_cq {
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/* data path - accessed per cqe */
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struct mlx5_cqwq wq;
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/* data path - accessed per napi poll */
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u16 event_ctr;
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struct napi_struct *napi;
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struct mlx5_core_cq mcq;
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struct mlx5e_channel *channel;
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struct mlx5e_priv *priv;
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/* cqe decompression */
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struct mlx5_cqe64 title;
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struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
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u8 mini_arr_idx;
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u16 decmprs_left;
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u16 decmprs_wqe_counter;
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/* control */
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struct mlx5_wq_ctrl wq_ctrl;
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} ____cacheline_aligned_in_smp;
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struct mlx5e_rq;
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typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
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struct mlx5_cqe64 *cqe);
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typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
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u16 ix);
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struct mlx5e_dma_info {
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struct page *page;
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dma_addr_t addr;
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};
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struct mlx5e_rx_am_stats {
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int ppms; /* packets per msec */
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int epms; /* events per msec */
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};
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struct mlx5e_rx_am_sample {
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ktime_t time;
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unsigned int pkt_ctr;
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u16 event_ctr;
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};
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struct mlx5e_rx_am { /* Adaptive Moderation */
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u8 state;
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struct mlx5e_rx_am_stats prev_stats;
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struct mlx5e_rx_am_sample start_sample;
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struct work_struct work;
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u8 profile_ix;
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u8 mode;
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u8 tune_state;
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u8 steps_right;
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u8 steps_left;
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u8 tired;
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};
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struct mlx5e_rq {
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/* data path */
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struct mlx5_wq_ll wq;
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u32 wqe_sz;
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struct sk_buff **skb;
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struct mlx5e_mpw_info *wqe_info;
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__be32 mkey_be;
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__be32 umr_mkey_be;
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struct device *pdev;
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struct net_device *netdev;
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struct mlx5e_tstamp *tstamp;
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struct mlx5e_rq_stats stats;
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struct mlx5e_cq cq;
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mlx5e_fp_handle_rx_cqe handle_rx_cqe;
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mlx5e_fp_alloc_wqe alloc_wqe;
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unsigned long state;
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int ix;
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struct mlx5e_rx_am am; /* Adaptive Moderation */
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/* control */
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struct mlx5_wq_ctrl wq_ctrl;
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u8 wq_type;
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u32 mpwqe_stride_sz;
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u32 mpwqe_num_strides;
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u32 rqn;
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struct mlx5e_channel *channel;
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struct mlx5e_priv *priv;
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} ____cacheline_aligned_in_smp;
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struct mlx5e_umr_dma_info {
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__be64 *mtt;
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__be64 *mtt_no_align;
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dma_addr_t mtt_addr;
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struct mlx5e_dma_info *dma_info;
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};
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struct mlx5e_mpw_info {
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union {
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struct mlx5e_dma_info dma_info;
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struct mlx5e_umr_dma_info umr;
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};
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u16 consumed_strides;
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u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
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void (*dma_pre_sync)(struct device *pdev,
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struct mlx5e_mpw_info *wi,
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u32 wqe_offset, u32 len);
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void (*add_skb_frag)(struct mlx5e_rq *rq,
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struct sk_buff *skb,
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struct mlx5e_mpw_info *wi,
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u32 page_idx, u32 frag_offset, u32 len);
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void (*copy_skb_header)(struct device *pdev,
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struct sk_buff *skb,
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struct mlx5e_mpw_info *wi,
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u32 page_idx, u32 offset,
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u32 headlen);
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void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
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};
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struct mlx5e_tx_wqe_info {
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u32 num_bytes;
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u8 num_wqebbs;
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u8 num_dma;
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};
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enum mlx5e_dma_map_type {
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MLX5E_DMA_MAP_SINGLE,
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MLX5E_DMA_MAP_PAGE
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};
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struct mlx5e_sq_dma {
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dma_addr_t addr;
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u32 size;
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enum mlx5e_dma_map_type type;
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};
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enum {
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MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
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MLX5E_SQ_STATE_BF_ENABLE,
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};
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struct mlx5e_ico_wqe_info {
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u8 opcode;
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u8 num_wqebbs;
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};
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struct mlx5e_sq {
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/* data path */
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/* dirtied @completion */
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u16 cc;
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u32 dma_fifo_cc;
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/* dirtied @xmit */
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u16 pc ____cacheline_aligned_in_smp;
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u32 dma_fifo_pc;
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u16 bf_offset;
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u16 prev_cc;
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u8 bf_budget;
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struct mlx5e_sq_stats stats;
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struct mlx5e_cq cq;
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/* pointers to per packet info: write@xmit, read@completion */
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struct sk_buff **skb;
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struct mlx5e_sq_dma *dma_fifo;
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struct mlx5e_tx_wqe_info *wqe_info;
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/* read only */
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struct mlx5_wq_cyc wq;
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u32 dma_fifo_mask;
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void __iomem *uar_map;
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struct netdev_queue *txq;
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u32 sqn;
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u16 bf_buf_size;
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u16 max_inline;
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u16 edge;
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struct device *pdev;
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struct mlx5e_tstamp *tstamp;
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__be32 mkey_be;
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unsigned long state;
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/* control path */
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5_uar uar;
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struct mlx5e_channel *channel;
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int tc;
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struct mlx5e_ico_wqe_info *ico_wqe_info;
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u32 rate_limit;
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} ____cacheline_aligned_in_smp;
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static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
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{
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return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
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(sq->cc == sq->pc));
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}
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enum channel_flags {
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MLX5E_CHANNEL_NAPI_SCHED = 1,
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};
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struct mlx5e_channel {
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/* data path */
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struct mlx5e_rq rq;
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struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
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struct mlx5e_sq icosq; /* internal control operations */
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struct napi_struct napi;
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struct device *pdev;
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struct net_device *netdev;
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__be32 mkey_be;
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u8 num_tc;
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unsigned long flags;
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/* control */
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struct mlx5e_priv *priv;
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int ix;
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int cpu;
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};
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enum mlx5e_traffic_types {
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MLX5E_TT_IPV4_TCP,
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MLX5E_TT_IPV6_TCP,
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MLX5E_TT_IPV4_UDP,
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MLX5E_TT_IPV6_UDP,
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MLX5E_TT_IPV4_IPSEC_AH,
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MLX5E_TT_IPV6_IPSEC_AH,
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MLX5E_TT_IPV4_IPSEC_ESP,
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MLX5E_TT_IPV6_IPSEC_ESP,
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MLX5E_TT_IPV4,
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MLX5E_TT_IPV6,
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MLX5E_TT_ANY,
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MLX5E_NUM_TT,
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MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
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};
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enum {
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MLX5E_STATE_ASYNC_EVENTS_ENABLE,
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MLX5E_STATE_OPENED,
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MLX5E_STATE_DESTROYING,
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};
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struct mlx5e_vxlan_db {
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spinlock_t lock; /* protect vxlan table */
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struct radix_tree_root tree;
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};
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|
|
struct mlx5e_l2_rule {
|
|
u8 addr[ETH_ALEN + 2];
|
|
struct mlx5_flow_rule *rule;
|
|
};
|
|
|
|
struct mlx5e_flow_table {
|
|
int num_groups;
|
|
struct mlx5_flow_table *t;
|
|
struct mlx5_flow_group **g;
|
|
};
|
|
|
|
#define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
|
|
|
|
struct mlx5e_tc_table {
|
|
struct mlx5_flow_table *t;
|
|
|
|
struct rhashtable_params ht_params;
|
|
struct rhashtable ht;
|
|
};
|
|
|
|
struct mlx5e_vlan_table {
|
|
struct mlx5e_flow_table ft;
|
|
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
|
|
struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
|
|
struct mlx5_flow_rule *untagged_rule;
|
|
struct mlx5_flow_rule *any_vlan_rule;
|
|
bool filter_disabled;
|
|
};
|
|
|
|
struct mlx5e_l2_table {
|
|
struct mlx5e_flow_table ft;
|
|
struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
|
|
struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
|
|
struct mlx5e_l2_rule broadcast;
|
|
struct mlx5e_l2_rule allmulti;
|
|
struct mlx5e_l2_rule promisc;
|
|
bool broadcast_enabled;
|
|
bool allmulti_enabled;
|
|
bool promisc_enabled;
|
|
};
|
|
|
|
/* L3/L4 traffic type classifier */
|
|
struct mlx5e_ttc_table {
|
|
struct mlx5e_flow_table ft;
|
|
struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
|
|
};
|
|
|
|
#define ARFS_HASH_SHIFT BITS_PER_BYTE
|
|
#define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
|
|
struct arfs_table {
|
|
struct mlx5e_flow_table ft;
|
|
struct mlx5_flow_rule *default_rule;
|
|
struct hlist_head rules_hash[ARFS_HASH_SIZE];
|
|
};
|
|
|
|
enum arfs_type {
|
|
ARFS_IPV4_TCP,
|
|
ARFS_IPV6_TCP,
|
|
ARFS_IPV4_UDP,
|
|
ARFS_IPV6_UDP,
|
|
ARFS_NUM_TYPES,
|
|
};
|
|
|
|
struct mlx5e_arfs_tables {
|
|
struct arfs_table arfs_tables[ARFS_NUM_TYPES];
|
|
/* Protect aRFS rules list */
|
|
spinlock_t arfs_lock;
|
|
struct list_head rules;
|
|
int last_filter_id;
|
|
struct workqueue_struct *wq;
|
|
};
|
|
|
|
/* NIC prio FTS */
|
|
enum {
|
|
MLX5E_VLAN_FT_LEVEL = 0,
|
|
MLX5E_L2_FT_LEVEL,
|
|
MLX5E_TTC_FT_LEVEL,
|
|
MLX5E_ARFS_FT_LEVEL
|
|
};
|
|
|
|
struct mlx5e_flow_steering {
|
|
struct mlx5_flow_namespace *ns;
|
|
struct mlx5e_tc_table tc;
|
|
struct mlx5e_vlan_table vlan;
|
|
struct mlx5e_l2_table l2;
|
|
struct mlx5e_ttc_table ttc;
|
|
struct mlx5e_arfs_tables arfs;
|
|
};
|
|
|
|
struct mlx5e_direct_tir {
|
|
u32 tirn;
|
|
u32 rqtn;
|
|
};
|
|
|
|
enum {
|
|
MLX5E_TC_PRIO = 0,
|
|
MLX5E_NIC_PRIO
|
|
};
|
|
|
|
struct mlx5e_priv {
|
|
/* priv data path fields - start */
|
|
struct mlx5e_sq **txq_to_sq_map;
|
|
int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
|
|
/* priv data path fields - end */
|
|
|
|
unsigned long state;
|
|
struct mutex state_lock; /* Protects Interface state */
|
|
struct mlx5_uar cq_uar;
|
|
u32 pdn;
|
|
u32 tdn;
|
|
struct mlx5_core_mkey mkey;
|
|
struct mlx5_core_mkey umr_mkey;
|
|
struct mlx5e_rq drop_rq;
|
|
|
|
struct mlx5e_channel **channel;
|
|
u32 tisn[MLX5E_MAX_NUM_TC];
|
|
u32 indir_rqtn;
|
|
u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
|
|
struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
|
|
u32 tx_rates[MLX5E_MAX_NUM_SQS];
|
|
|
|
struct mlx5e_flow_steering fs;
|
|
struct mlx5e_vxlan_db vxlan;
|
|
|
|
struct mlx5e_params params;
|
|
struct workqueue_struct *wq;
|
|
struct work_struct update_carrier_work;
|
|
struct work_struct set_rx_mode_work;
|
|
struct delayed_work update_stats_work;
|
|
|
|
u32 pflags;
|
|
struct mlx5_core_dev *mdev;
|
|
struct net_device *netdev;
|
|
struct mlx5e_stats stats;
|
|
struct mlx5e_tstamp tstamp;
|
|
u16 q_counter;
|
|
};
|
|
|
|
enum mlx5e_link_mode {
|
|
MLX5E_1000BASE_CX_SGMII = 0,
|
|
MLX5E_1000BASE_KX = 1,
|
|
MLX5E_10GBASE_CX4 = 2,
|
|
MLX5E_10GBASE_KX4 = 3,
|
|
MLX5E_10GBASE_KR = 4,
|
|
MLX5E_20GBASE_KR2 = 5,
|
|
MLX5E_40GBASE_CR4 = 6,
|
|
MLX5E_40GBASE_KR4 = 7,
|
|
MLX5E_56GBASE_R4 = 8,
|
|
MLX5E_10GBASE_CR = 12,
|
|
MLX5E_10GBASE_SR = 13,
|
|
MLX5E_10GBASE_ER = 14,
|
|
MLX5E_40GBASE_SR4 = 15,
|
|
MLX5E_40GBASE_LR4 = 16,
|
|
MLX5E_100GBASE_CR4 = 20,
|
|
MLX5E_100GBASE_SR4 = 21,
|
|
MLX5E_100GBASE_KR4 = 22,
|
|
MLX5E_100GBASE_LR4 = 23,
|
|
MLX5E_100BASE_TX = 24,
|
|
MLX5E_1000BASE_T = 25,
|
|
MLX5E_10GBASE_T = 26,
|
|
MLX5E_25GBASE_CR = 27,
|
|
MLX5E_25GBASE_KR = 28,
|
|
MLX5E_25GBASE_SR = 29,
|
|
MLX5E_50GBASE_CR2 = 30,
|
|
MLX5E_50GBASE_KR2 = 31,
|
|
MLX5E_LINK_MODES_NUMBER,
|
|
};
|
|
|
|
#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
|
|
|
|
void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
|
|
u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
|
|
void *accel_priv, select_queue_fallback_t fallback);
|
|
netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
|
|
|
|
void mlx5e_completion_event(struct mlx5_core_cq *mcq);
|
|
void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
|
|
int mlx5e_napi_poll(struct napi_struct *napi, int budget);
|
|
bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
|
|
int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
|
|
|
|
void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
|
|
void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
|
|
bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
|
|
int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
|
|
int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
|
|
void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
|
|
void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
|
|
struct mlx5_cqe64 *cqe,
|
|
u16 byte_cnt,
|
|
struct mlx5e_mpw_info *wi,
|
|
struct sk_buff *skb);
|
|
void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
|
|
struct mlx5_cqe64 *cqe,
|
|
u16 byte_cnt,
|
|
struct mlx5e_mpw_info *wi,
|
|
struct sk_buff *skb);
|
|
void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
|
|
struct mlx5e_mpw_info *wi);
|
|
void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
|
|
struct mlx5e_mpw_info *wi);
|
|
struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
|
|
|
|
void mlx5e_rx_am(struct mlx5e_rq *rq);
|
|
void mlx5e_rx_am_work(struct work_struct *work);
|
|
struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
|
|
|
|
void mlx5e_update_stats(struct mlx5e_priv *priv);
|
|
|
|
int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
|
|
void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
|
|
void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
|
|
void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
|
|
void mlx5e_set_rx_mode_work(struct work_struct *work);
|
|
|
|
void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
|
|
struct skb_shared_hwtstamps *hwts);
|
|
void mlx5e_timestamp_init(struct mlx5e_priv *priv);
|
|
void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
|
|
int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
|
|
int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
|
|
void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
|
|
|
|
int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
|
|
u16 vid);
|
|
int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
|
|
u16 vid);
|
|
void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
|
|
void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
|
|
|
|
int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
|
|
|
|
int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
|
|
void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
|
|
|
|
int mlx5e_open_locked(struct net_device *netdev);
|
|
int mlx5e_close_locked(struct net_device *netdev);
|
|
void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
|
|
u32 *indirection_rqt, int len,
|
|
int num_channels);
|
|
int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
|
|
|
|
void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
|
|
u8 cq_period_mode);
|
|
|
|
static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
|
|
struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
|
|
{
|
|
u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
|
|
|
|
/* ensure wqe is visible to device before updating doorbell record */
|
|
dma_wmb();
|
|
|
|
*sq->wq.db = cpu_to_be32(sq->pc);
|
|
|
|
/* ensure doorbell record is visible to device before ringing the
|
|
* doorbell
|
|
*/
|
|
wmb();
|
|
if (bf_sz)
|
|
__iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
|
|
else
|
|
mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
|
|
/* flush the write-combining mapped buffer */
|
|
wmb();
|
|
|
|
sq->bf_offset ^= sq->bf_buf_size;
|
|
}
|
|
|
|
static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
|
|
{
|
|
struct mlx5_core_cq *mcq;
|
|
|
|
mcq = &cq->mcq;
|
|
mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
|
|
}
|
|
|
|
static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
|
|
{
|
|
return min_t(int, mdev->priv.eq_table.num_comp_vectors,
|
|
MLX5E_MAX_NUM_CHANNELS);
|
|
}
|
|
|
|
static inline int mlx5e_get_mtt_octw(int npages)
|
|
{
|
|
return ALIGN(npages, 8) / 2;
|
|
}
|
|
|
|
extern const struct ethtool_ops mlx5e_ethtool_ops;
|
|
#ifdef CONFIG_MLX5_CORE_EN_DCB
|
|
extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
|
|
int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
|
|
#endif
|
|
|
|
#ifndef CONFIG_RFS_ACCEL
|
|
static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
|
|
|
|
static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
|
|
{
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
|
|
{
|
|
return -ENOTSUPP;
|
|
}
|
|
#else
|
|
int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
|
|
void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
|
|
int mlx5e_arfs_enable(struct mlx5e_priv *priv);
|
|
int mlx5e_arfs_disable(struct mlx5e_priv *priv);
|
|
int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
|
|
u16 rxq_index, u32 flow_id);
|
|
#endif
|
|
|
|
u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
|
|
|
|
#endif /* __MLX5_EN_H__ */
|