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![Jonathan Cameron](/assets/img/avatar_default.png)
____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_DMA_MINALIGN definition.
Fixes: 327a0eaf19
("iio: accel: adxl355: Add triggered buffer support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Puranjay Mohan <puranjay12@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-4-jic23@kernel.org
761 lines
18 KiB
C
761 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ADXL355 3-Axis Digital Accelerometer IIO core driver
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*
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* Copyright (c) 2021 Puranjay Mohan <puranjay12@gmail.com>
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*
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* Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/adxl354_adxl355.pdf
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*/
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/limits.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/units.h>
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#include <asm/unaligned.h>
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#include "adxl355.h"
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/* ADXL355 Register Definitions */
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#define ADXL355_DEVID_AD_REG 0x00
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#define ADXL355_DEVID_MST_REG 0x01
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#define ADXL355_PARTID_REG 0x02
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#define ADXL355_STATUS_REG 0x04
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#define ADXL355_FIFO_ENTRIES_REG 0x05
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#define ADXL355_TEMP2_REG 0x06
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#define ADXL355_XDATA3_REG 0x08
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#define ADXL355_YDATA3_REG 0x0B
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#define ADXL355_ZDATA3_REG 0x0E
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#define ADXL355_FIFO_DATA_REG 0x11
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#define ADXL355_OFFSET_X_H_REG 0x1E
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#define ADXL355_OFFSET_Y_H_REG 0x20
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#define ADXL355_OFFSET_Z_H_REG 0x22
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#define ADXL355_ACT_EN_REG 0x24
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#define ADXL355_ACT_THRESH_H_REG 0x25
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#define ADXL355_ACT_THRESH_L_REG 0x26
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#define ADXL355_ACT_COUNT_REG 0x27
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#define ADXL355_FILTER_REG 0x28
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#define ADXL355_FILTER_ODR_MSK GENMASK(3, 0)
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#define ADXL355_FILTER_HPF_MSK GENMASK(6, 4)
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#define ADXL355_FIFO_SAMPLES_REG 0x29
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#define ADXL355_INT_MAP_REG 0x2A
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#define ADXL355_SYNC_REG 0x2B
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#define ADXL355_RANGE_REG 0x2C
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#define ADXL355_POWER_CTL_REG 0x2D
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#define ADXL355_POWER_CTL_MODE_MSK GENMASK(1, 0)
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#define ADXL355_POWER_CTL_DRDY_MSK BIT(2)
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#define ADXL355_SELF_TEST_REG 0x2E
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#define ADXL355_RESET_REG 0x2F
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#define ADXL355_DEVID_AD_VAL 0xAD
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#define ADXL355_DEVID_MST_VAL 0x1D
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#define ADXL355_PARTID_VAL 0xED
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#define ADXL355_RESET_CODE 0x52
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static const struct regmap_range adxl355_read_reg_range[] = {
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regmap_reg_range(ADXL355_DEVID_AD_REG, ADXL355_FIFO_DATA_REG),
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regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_SELF_TEST_REG),
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};
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const struct regmap_access_table adxl355_readable_regs_tbl = {
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.yes_ranges = adxl355_read_reg_range,
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.n_yes_ranges = ARRAY_SIZE(adxl355_read_reg_range),
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};
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EXPORT_SYMBOL_NS_GPL(adxl355_readable_regs_tbl, IIO_ADXL355);
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static const struct regmap_range adxl355_write_reg_range[] = {
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regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_RESET_REG),
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};
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const struct regmap_access_table adxl355_writeable_regs_tbl = {
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.yes_ranges = adxl355_write_reg_range,
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.n_yes_ranges = ARRAY_SIZE(adxl355_write_reg_range),
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};
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EXPORT_SYMBOL_NS_GPL(adxl355_writeable_regs_tbl, IIO_ADXL355);
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enum adxl355_op_mode {
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ADXL355_MEASUREMENT,
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ADXL355_STANDBY,
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ADXL355_TEMP_OFF,
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};
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enum adxl355_odr {
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ADXL355_ODR_4000HZ,
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ADXL355_ODR_2000HZ,
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ADXL355_ODR_1000HZ,
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ADXL355_ODR_500HZ,
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ADXL355_ODR_250HZ,
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ADXL355_ODR_125HZ,
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ADXL355_ODR_62_5HZ,
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ADXL355_ODR_31_25HZ,
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ADXL355_ODR_15_625HZ,
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ADXL355_ODR_7_813HZ,
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ADXL355_ODR_3_906HZ,
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};
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enum adxl355_hpf_3db {
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ADXL355_HPF_OFF,
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ADXL355_HPF_24_7,
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ADXL355_HPF_6_2084,
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ADXL355_HPF_1_5545,
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ADXL355_HPF_0_3862,
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ADXL355_HPF_0_0954,
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ADXL355_HPF_0_0238,
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};
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static const int adxl355_odr_table[][2] = {
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[0] = {4000, 0},
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[1] = {2000, 0},
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[2] = {1000, 0},
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[3] = {500, 0},
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[4] = {250, 0},
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[5] = {125, 0},
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[6] = {62, 500000},
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[7] = {31, 250000},
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[8] = {15, 625000},
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[9] = {7, 813000},
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[10] = {3, 906000},
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};
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static const int adxl355_hpf_3db_multipliers[] = {
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0,
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247000,
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62084,
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15545,
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3862,
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954,
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238,
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};
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enum adxl355_chans {
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chan_x, chan_y, chan_z,
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};
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struct adxl355_chan_info {
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u8 data_reg;
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u8 offset_reg;
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};
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static const struct adxl355_chan_info adxl355_chans[] = {
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[chan_x] = {
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.data_reg = ADXL355_XDATA3_REG,
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.offset_reg = ADXL355_OFFSET_X_H_REG
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},
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[chan_y] = {
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.data_reg = ADXL355_YDATA3_REG,
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.offset_reg = ADXL355_OFFSET_Y_H_REG
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},
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[chan_z] = {
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.data_reg = ADXL355_ZDATA3_REG,
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.offset_reg = ADXL355_OFFSET_Z_H_REG
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},
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};
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struct adxl355_data {
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struct regmap *regmap;
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struct device *dev;
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struct mutex lock; /* lock to protect op_mode */
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enum adxl355_op_mode op_mode;
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enum adxl355_odr odr;
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enum adxl355_hpf_3db hpf_3db;
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int calibbias[3];
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int adxl355_hpf_3db_table[7][2];
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struct iio_trigger *dready_trig;
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union {
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u8 transf_buf[3];
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struct {
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u8 buf[14];
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s64 ts;
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} buffer;
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} __aligned(IIO_DMA_MINALIGN);
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};
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static int adxl355_set_op_mode(struct adxl355_data *data,
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enum adxl355_op_mode op_mode)
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{
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int ret;
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if (data->op_mode == op_mode)
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return 0;
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ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG,
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ADXL355_POWER_CTL_MODE_MSK, op_mode);
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if (ret)
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return ret;
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data->op_mode = op_mode;
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return ret;
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}
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static int adxl355_data_rdy_trigger_set_state(struct iio_trigger *trig,
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bool state)
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{
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struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
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struct adxl355_data *data = iio_priv(indio_dev);
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int ret;
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mutex_lock(&data->lock);
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ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG,
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ADXL355_POWER_CTL_DRDY_MSK,
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FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK,
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state ? 0 : 1));
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mutex_unlock(&data->lock);
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return ret;
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}
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static void adxl355_fill_3db_frequency_table(struct adxl355_data *data)
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{
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u32 multiplier;
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u64 div, rem;
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u64 odr;
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int i;
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odr = mul_u64_u32_shr(adxl355_odr_table[data->odr][0], MEGA, 0) +
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adxl355_odr_table[data->odr][1];
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for (i = 0; i < ARRAY_SIZE(adxl355_hpf_3db_multipliers); i++) {
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multiplier = adxl355_hpf_3db_multipliers[i];
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div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0),
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TERA * 100, &rem);
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data->adxl355_hpf_3db_table[i][0] = div;
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data->adxl355_hpf_3db_table[i][1] = div_u64(rem, MEGA * 100);
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}
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}
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static int adxl355_setup(struct adxl355_data *data)
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{
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unsigned int regval;
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int ret;
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ret = regmap_read(data->regmap, ADXL355_DEVID_AD_REG, ®val);
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if (ret)
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return ret;
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if (regval != ADXL355_DEVID_AD_VAL) {
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dev_err(data->dev, "Invalid ADI ID 0x%02x\n", regval);
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return -ENODEV;
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}
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ret = regmap_read(data->regmap, ADXL355_DEVID_MST_REG, ®val);
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if (ret)
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return ret;
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if (regval != ADXL355_DEVID_MST_VAL) {
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dev_err(data->dev, "Invalid MEMS ID 0x%02x\n", regval);
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return -ENODEV;
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}
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ret = regmap_read(data->regmap, ADXL355_PARTID_REG, ®val);
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if (ret)
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return ret;
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if (regval != ADXL355_PARTID_VAL) {
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dev_err(data->dev, "Invalid DEV ID 0x%02x\n", regval);
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return -ENODEV;
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}
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/*
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* Perform a software reset to make sure the device is in a consistent
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* state after start-up.
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*/
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ret = regmap_write(data->regmap, ADXL355_RESET_REG, ADXL355_RESET_CODE);
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if (ret)
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return ret;
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ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG,
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ADXL355_POWER_CTL_DRDY_MSK,
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FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 1));
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if (ret)
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return ret;
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adxl355_fill_3db_frequency_table(data);
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return adxl355_set_op_mode(data, ADXL355_MEASUREMENT);
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}
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static int adxl355_get_temp_data(struct adxl355_data *data, u8 addr)
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{
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return regmap_bulk_read(data->regmap, addr, data->transf_buf, 2);
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}
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static int adxl355_read_axis(struct adxl355_data *data, u8 addr)
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{
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int ret;
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ret = regmap_bulk_read(data->regmap, addr, data->transf_buf,
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ARRAY_SIZE(data->transf_buf));
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if (ret)
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return ret;
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return get_unaligned_be24(data->transf_buf);
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}
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static int adxl355_find_match(const int (*freq_tbl)[2], const int n,
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const int val, const int val2)
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{
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int i;
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for (i = 0; i < n; i++) {
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if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2)
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return i;
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}
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return -EINVAL;
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}
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static int adxl355_set_odr(struct adxl355_data *data,
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enum adxl355_odr odr)
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{
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int ret;
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mutex_lock(&data->lock);
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if (data->odr == odr) {
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mutex_unlock(&data->lock);
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return 0;
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}
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ret = adxl355_set_op_mode(data, ADXL355_STANDBY);
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if (ret)
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goto err_unlock;
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ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG,
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ADXL355_FILTER_ODR_MSK,
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FIELD_PREP(ADXL355_FILTER_ODR_MSK, odr));
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if (ret)
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goto err_set_opmode;
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data->odr = odr;
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adxl355_fill_3db_frequency_table(data);
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ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT);
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if (ret)
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goto err_set_opmode;
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mutex_unlock(&data->lock);
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return 0;
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err_set_opmode:
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adxl355_set_op_mode(data, ADXL355_MEASUREMENT);
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err_unlock:
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mutex_unlock(&data->lock);
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return ret;
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}
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static int adxl355_set_hpf_3db(struct adxl355_data *data,
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enum adxl355_hpf_3db hpf)
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{
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int ret;
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mutex_lock(&data->lock);
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if (data->hpf_3db == hpf) {
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mutex_unlock(&data->lock);
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return 0;
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}
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ret = adxl355_set_op_mode(data, ADXL355_STANDBY);
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if (ret)
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goto err_unlock;
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ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG,
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ADXL355_FILTER_HPF_MSK,
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FIELD_PREP(ADXL355_FILTER_HPF_MSK, hpf));
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if (ret)
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goto err_set_opmode;
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data->hpf_3db = hpf;
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ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT);
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if (ret)
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goto err_set_opmode;
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mutex_unlock(&data->lock);
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return 0;
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err_set_opmode:
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adxl355_set_op_mode(data, ADXL355_MEASUREMENT);
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err_unlock:
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mutex_unlock(&data->lock);
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return ret;
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}
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static int adxl355_set_calibbias(struct adxl355_data *data,
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enum adxl355_chans chan, int calibbias)
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{
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int ret;
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mutex_lock(&data->lock);
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ret = adxl355_set_op_mode(data, ADXL355_STANDBY);
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if (ret)
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goto err_unlock;
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put_unaligned_be16(calibbias, data->transf_buf);
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ret = regmap_bulk_write(data->regmap,
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adxl355_chans[chan].offset_reg,
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data->transf_buf, 2);
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if (ret)
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goto err_set_opmode;
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data->calibbias[chan] = calibbias;
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ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT);
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if (ret)
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goto err_set_opmode;
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mutex_unlock(&data->lock);
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return 0;
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err_set_opmode:
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adxl355_set_op_mode(data, ADXL355_MEASUREMENT);
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err_unlock:
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mutex_unlock(&data->lock);
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return ret;
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}
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static int adxl355_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct adxl355_data *data = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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switch (chan->type) {
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case IIO_TEMP:
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ret = adxl355_get_temp_data(data, chan->address);
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if (ret < 0)
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return ret;
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*val = get_unaligned_be16(data->transf_buf);
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return IIO_VAL_INT;
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case IIO_ACCEL:
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ret = adxl355_read_axis(data, adxl355_chans[
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chan->address].data_reg);
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if (ret < 0)
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return ret;
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*val = sign_extend32(ret >> chan->scan_type.shift,
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chan->scan_type.realbits - 1);
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_SCALE:
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switch (chan->type) {
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/*
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* The datasheet defines an intercept of 1885 LSB at 25 degC
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* and a slope of -9.05 LSB/C. The following formula can be used
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* to find the temperature:
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* Temp = ((RAW - 1885)/(-9.05)) + 25 but this doesn't follow
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* the format of the IIO which is Temp = (RAW + OFFSET) * SCALE.
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* Hence using some rearranging we get the scale as -110.497238
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* and offset as -2111.25.
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*/
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case IIO_TEMP:
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*val = -110;
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*val2 = 497238;
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return IIO_VAL_INT_PLUS_MICRO;
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/*
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* At +/- 2g with 20-bit resolution, scale is given in datasheet
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* as 3.9ug/LSB = 0.0000039 * 9.80665 = 0.00003824593 m/s^2.
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*/
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case IIO_ACCEL:
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*val = 0;
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*val2 = 38245;
|
|
return IIO_VAL_INT_PLUS_NANO;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
case IIO_CHAN_INFO_OFFSET:
|
|
*val = -2111;
|
|
*val2 = 250000;
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
|
case IIO_CHAN_INFO_CALIBBIAS:
|
|
*val = sign_extend32(data->calibbias[chan->address], 15);
|
|
return IIO_VAL_INT;
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
*val = adxl355_odr_table[data->odr][0];
|
|
*val2 = adxl355_odr_table[data->odr][1];
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
|
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
|
|
*val = data->adxl355_hpf_3db_table[data->hpf_3db][0];
|
|
*val2 = data->adxl355_hpf_3db_table[data->hpf_3db][1];
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int adxl355_write_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int val, int val2, long mask)
|
|
{
|
|
struct adxl355_data *data = iio_priv(indio_dev);
|
|
int odr_idx, hpf_idx, calibbias;
|
|
|
|
switch (mask) {
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
odr_idx = adxl355_find_match(adxl355_odr_table,
|
|
ARRAY_SIZE(adxl355_odr_table),
|
|
val, val2);
|
|
if (odr_idx < 0)
|
|
return odr_idx;
|
|
|
|
return adxl355_set_odr(data, odr_idx);
|
|
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
|
|
hpf_idx = adxl355_find_match(data->adxl355_hpf_3db_table,
|
|
ARRAY_SIZE(data->adxl355_hpf_3db_table),
|
|
val, val2);
|
|
if (hpf_idx < 0)
|
|
return hpf_idx;
|
|
|
|
return adxl355_set_hpf_3db(data, hpf_idx);
|
|
case IIO_CHAN_INFO_CALIBBIAS:
|
|
calibbias = clamp_t(int, val, S16_MIN, S16_MAX);
|
|
|
|
return adxl355_set_calibbias(data, chan->address, calibbias);
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int adxl355_read_avail(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
const int **vals, int *type, int *length,
|
|
long mask)
|
|
{
|
|
struct adxl355_data *data = iio_priv(indio_dev);
|
|
|
|
switch (mask) {
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
*vals = (const int *)adxl355_odr_table;
|
|
*type = IIO_VAL_INT_PLUS_MICRO;
|
|
/* Values are stored in a 2D matrix */
|
|
*length = ARRAY_SIZE(adxl355_odr_table) * 2;
|
|
|
|
return IIO_AVAIL_LIST;
|
|
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
|
|
*vals = (const int *)data->adxl355_hpf_3db_table;
|
|
*type = IIO_VAL_INT_PLUS_MICRO;
|
|
/* Values are stored in a 2D matrix */
|
|
*length = ARRAY_SIZE(data->adxl355_hpf_3db_table) * 2;
|
|
|
|
return IIO_AVAIL_LIST;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static const unsigned long adxl355_avail_scan_masks[] = {
|
|
GENMASK(3, 0),
|
|
0
|
|
};
|
|
|
|
static const struct iio_info adxl355_info = {
|
|
.read_raw = adxl355_read_raw,
|
|
.write_raw = adxl355_write_raw,
|
|
.read_avail = &adxl355_read_avail,
|
|
};
|
|
|
|
static const struct iio_trigger_ops adxl355_trigger_ops = {
|
|
.set_trigger_state = &adxl355_data_rdy_trigger_set_state,
|
|
.validate_device = &iio_trigger_validate_own_device,
|
|
};
|
|
|
|
static irqreturn_t adxl355_trigger_handler(int irq, void *p)
|
|
{
|
|
struct iio_poll_func *pf = p;
|
|
struct iio_dev *indio_dev = pf->indio_dev;
|
|
struct adxl355_data *data = iio_priv(indio_dev);
|
|
int ret;
|
|
|
|
mutex_lock(&data->lock);
|
|
|
|
/*
|
|
* data->buffer is used both for triggered buffer support
|
|
* and read/write_raw(), hence, it has to be zeroed here before usage.
|
|
*/
|
|
data->buffer.buf[0] = 0;
|
|
|
|
/*
|
|
* The acceleration data is 24 bits and big endian. It has to be saved
|
|
* in 32 bits, hence, it is saved in the 2nd byte of the 4 byte buffer.
|
|
* The buf array is 14 bytes as it includes 3x4=12 bytes for
|
|
* accelaration data of x, y, and z axis. It also includes 2 bytes for
|
|
* temperature data.
|
|
*/
|
|
ret = regmap_bulk_read(data->regmap, ADXL355_XDATA3_REG,
|
|
&data->buffer.buf[1], 3);
|
|
if (ret)
|
|
goto out_unlock_notify;
|
|
|
|
ret = regmap_bulk_read(data->regmap, ADXL355_YDATA3_REG,
|
|
&data->buffer.buf[5], 3);
|
|
if (ret)
|
|
goto out_unlock_notify;
|
|
|
|
ret = regmap_bulk_read(data->regmap, ADXL355_ZDATA3_REG,
|
|
&data->buffer.buf[9], 3);
|
|
if (ret)
|
|
goto out_unlock_notify;
|
|
|
|
ret = regmap_bulk_read(data->regmap, ADXL355_TEMP2_REG,
|
|
&data->buffer.buf[12], 2);
|
|
if (ret)
|
|
goto out_unlock_notify;
|
|
|
|
iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
|
|
pf->timestamp);
|
|
|
|
out_unlock_notify:
|
|
mutex_unlock(&data->lock);
|
|
iio_trigger_notify_done(indio_dev->trig);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#define ADXL355_ACCEL_CHANNEL(index, reg, axis) { \
|
|
.type = IIO_ACCEL, \
|
|
.address = reg, \
|
|
.modified = 1, \
|
|
.channel2 = IIO_MOD_##axis, \
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
|
|
BIT(IIO_CHAN_INFO_CALIBBIAS), \
|
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
|
|
BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
|
|
BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
|
|
.info_mask_shared_by_type_available = \
|
|
BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
|
|
BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
|
|
.scan_index = index, \
|
|
.scan_type = { \
|
|
.sign = 's', \
|
|
.realbits = 20, \
|
|
.storagebits = 32, \
|
|
.shift = 4, \
|
|
.endianness = IIO_BE, \
|
|
} \
|
|
}
|
|
|
|
static const struct iio_chan_spec adxl355_channels[] = {
|
|
ADXL355_ACCEL_CHANNEL(0, chan_x, X),
|
|
ADXL355_ACCEL_CHANNEL(1, chan_y, Y),
|
|
ADXL355_ACCEL_CHANNEL(2, chan_z, Z),
|
|
{
|
|
.type = IIO_TEMP,
|
|
.address = ADXL355_TEMP2_REG,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_SCALE) |
|
|
BIT(IIO_CHAN_INFO_OFFSET),
|
|
.scan_index = 3,
|
|
.scan_type = {
|
|
.sign = 's',
|
|
.realbits = 12,
|
|
.storagebits = 16,
|
|
.endianness = IIO_BE,
|
|
},
|
|
},
|
|
IIO_CHAN_SOFT_TIMESTAMP(4),
|
|
};
|
|
|
|
static int adxl355_probe_trigger(struct iio_dev *indio_dev, int irq)
|
|
{
|
|
struct adxl355_data *data = iio_priv(indio_dev);
|
|
int ret;
|
|
|
|
data->dready_trig = devm_iio_trigger_alloc(data->dev, "%s-dev%d",
|
|
indio_dev->name,
|
|
iio_device_id(indio_dev));
|
|
if (!data->dready_trig)
|
|
return -ENOMEM;
|
|
|
|
data->dready_trig->ops = &adxl355_trigger_ops;
|
|
iio_trigger_set_drvdata(data->dready_trig, indio_dev);
|
|
|
|
ret = devm_request_irq(data->dev, irq,
|
|
&iio_trigger_generic_data_rdy_poll,
|
|
IRQF_ONESHOT, "adxl355_irq", data->dready_trig);
|
|
if (ret)
|
|
return dev_err_probe(data->dev, ret, "request irq %d failed\n",
|
|
irq);
|
|
|
|
ret = devm_iio_trigger_register(data->dev, data->dready_trig);
|
|
if (ret) {
|
|
dev_err(data->dev, "iio trigger register failed\n");
|
|
return ret;
|
|
}
|
|
|
|
indio_dev->trig = iio_trigger_get(data->dready_trig);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int adxl355_core_probe(struct device *dev, struct regmap *regmap,
|
|
const char *name)
|
|
{
|
|
struct adxl355_data *data;
|
|
struct iio_dev *indio_dev;
|
|
int ret;
|
|
int irq;
|
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
data = iio_priv(indio_dev);
|
|
data->regmap = regmap;
|
|
data->dev = dev;
|
|
data->op_mode = ADXL355_STANDBY;
|
|
mutex_init(&data->lock);
|
|
|
|
indio_dev->name = name;
|
|
indio_dev->info = &adxl355_info;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->channels = adxl355_channels;
|
|
indio_dev->num_channels = ARRAY_SIZE(adxl355_channels);
|
|
indio_dev->available_scan_masks = adxl355_avail_scan_masks;
|
|
|
|
ret = adxl355_setup(data);
|
|
if (ret) {
|
|
dev_err(dev, "ADXL355 setup failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
|
|
&iio_pollfunc_store_time,
|
|
&adxl355_trigger_handler, NULL);
|
|
if (ret) {
|
|
dev_err(dev, "iio triggered buffer setup failed\n");
|
|
return ret;
|
|
}
|
|
|
|
irq = fwnode_irq_get_byname(dev_fwnode(dev), "DRDY");
|
|
if (irq > 0) {
|
|
ret = adxl355_probe_trigger(indio_dev, irq);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return devm_iio_device_register(dev, indio_dev);
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(adxl355_core_probe, IIO_ADXL355);
|
|
|
|
MODULE_AUTHOR("Puranjay Mohan <puranjay12@gmail.com>");
|
|
MODULE_DESCRIPTION("ADXL355 3-Axis Digital Accelerometer core driver");
|
|
MODULE_LICENSE("GPL v2");
|