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![Jonathan Cameron](/assets/img/avatar_default.png)
____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_DMA_MINALIGN definition.
Update comment to reflect that DMA safety may require separate
cachelines.
Fixes: cbab791c5e
("iio: accel: add ADXL367 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <demonsingur@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-5-jic23@kernel.org
166 lines
4.3 KiB
C
166 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Analog Devices, Inc.
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* Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
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*/
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/iio/iio.h>
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#include "adxl367.h"
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#define ADXL367_SPI_WRITE_COMMAND 0x0A
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#define ADXL367_SPI_READ_COMMAND 0x0B
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#define ADXL367_SPI_FIFO_COMMAND 0x0D
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struct adxl367_spi_state {
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struct spi_device *spi;
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struct spi_message reg_write_msg;
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struct spi_transfer reg_write_xfer[2];
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struct spi_message reg_read_msg;
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struct spi_transfer reg_read_xfer[2];
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struct spi_message fifo_msg;
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struct spi_transfer fifo_xfer[2];
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/*
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* DMA (thus cache coherency maintenance) may require the
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* transfer buffers live in their own cache lines.
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*/
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u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
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u8 reg_read_tx_buf[2];
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u8 fifo_tx_buf[1];
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};
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static int adxl367_read_fifo(void *context, __be16 *fifo_buf,
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unsigned int fifo_entries)
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{
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struct adxl367_spi_state *st = context;
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st->fifo_xfer[1].rx_buf = fifo_buf;
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st->fifo_xfer[1].len = fifo_entries * sizeof(*fifo_buf);
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return spi_sync(st->spi, &st->fifo_msg);
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}
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static int adxl367_read(void *context, const void *reg_buf, size_t reg_size,
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void *val_buf, size_t val_size)
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{
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struct adxl367_spi_state *st = context;
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u8 reg = ((const u8 *)reg_buf)[0];
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st->reg_read_tx_buf[1] = reg;
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st->reg_read_xfer[1].rx_buf = val_buf;
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st->reg_read_xfer[1].len = val_size;
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return spi_sync(st->spi, &st->reg_read_msg);
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}
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static int adxl367_write(void *context, const void *val_buf, size_t val_size)
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{
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struct adxl367_spi_state *st = context;
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st->reg_write_xfer[1].tx_buf = val_buf;
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st->reg_write_xfer[1].len = val_size;
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return spi_sync(st->spi, &st->reg_write_msg);
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}
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static struct regmap_bus adxl367_spi_regmap_bus = {
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.read = adxl367_read,
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.write = adxl367_write,
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};
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static const struct regmap_config adxl367_spi_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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};
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static const struct adxl367_ops adxl367_spi_ops = {
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.read_fifo = adxl367_read_fifo,
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};
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static int adxl367_spi_probe(struct spi_device *spi)
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{
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struct adxl367_spi_state *st;
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struct regmap *regmap;
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st = devm_kzalloc(&spi->dev, sizeof(*st), GFP_KERNEL);
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if (!st)
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return -ENOMEM;
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st->spi = spi;
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/*
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* Xfer: [XFR1] [ XFR2 ]
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* Master: 0x0A ADDR DATA0 DATA1 ... DATAN
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* Slave: .... ..........................
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*/
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st->reg_write_tx_buf[0] = ADXL367_SPI_WRITE_COMMAND;
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st->reg_write_xfer[0].tx_buf = st->reg_write_tx_buf;
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st->reg_write_xfer[0].len = sizeof(st->reg_write_tx_buf);
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spi_message_init_with_transfers(&st->reg_write_msg,
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st->reg_write_xfer, 2);
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/*
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* Xfer: [ XFR1 ] [ XFR2 ]
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* Master: 0x0B ADDR .....................
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* Slave: ......... DATA0 DATA1 ... DATAN
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*/
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st->reg_read_tx_buf[0] = ADXL367_SPI_READ_COMMAND;
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st->reg_read_xfer[0].tx_buf = st->reg_read_tx_buf;
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st->reg_read_xfer[0].len = sizeof(st->reg_read_tx_buf);
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spi_message_init_with_transfers(&st->reg_read_msg,
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st->reg_read_xfer, 2);
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/*
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* Xfer: [XFR1] [ XFR2 ]
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* Master: 0x0D .....................
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* Slave: .... DATA0 DATA1 ... DATAN
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*/
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st->fifo_tx_buf[0] = ADXL367_SPI_FIFO_COMMAND;
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st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
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st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
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spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, 2);
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regmap = devm_regmap_init(&spi->dev, &adxl367_spi_regmap_bus, st,
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&adxl367_spi_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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return adxl367_probe(&spi->dev, &adxl367_spi_ops, st, regmap, spi->irq);
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}
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static const struct spi_device_id adxl367_spi_id[] = {
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{ "adxl367", 0 },
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{ },
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};
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MODULE_DEVICE_TABLE(spi, adxl367_spi_id);
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static const struct of_device_id adxl367_of_match[] = {
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{ .compatible = "adi,adxl367" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, adxl367_of_match);
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static struct spi_driver adxl367_spi_driver = {
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.driver = {
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.name = "adxl367_spi",
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.of_match_table = adxl367_of_match,
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},
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.probe = adxl367_spi_probe,
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.id_table = adxl367_spi_id,
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};
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module_spi_driver(adxl367_spi_driver);
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MODULE_IMPORT_NS(IIO_ADXL367);
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MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
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MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer SPI driver");
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MODULE_LICENSE("GPL");
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