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![Jonathan Cameron](/assets/img/avatar_default.png)
These macros allow the compiler to remove unused pm ops functions without needing to mark them maybe unused. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn> Cc: Mike Looijmans <mike.looijmans@topic.nl> Link: https://lore.kernel.org/r/20220807185618.1038812-6-jic23@kernel.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
632 lines
16 KiB
C
632 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
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* - BMI088
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*
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* Copyright (c) 2018-2021, Topic Embedded Products
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <asm/unaligned.h>
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#include "bmi088-accel.h"
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#define BMI088_ACCEL_REG_CHIP_ID 0x00
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#define BMI088_ACCEL_REG_ERROR 0x02
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#define BMI088_ACCEL_REG_INT_STATUS 0x1D
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#define BMI088_ACCEL_INT_STATUS_BIT_DRDY BIT(7)
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#define BMI088_ACCEL_REG_RESET 0x7E
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#define BMI088_ACCEL_RESET_VAL 0xB6
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#define BMI088_ACCEL_REG_PWR_CTRL 0x7D
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#define BMI088_ACCEL_REG_PWR_CONF 0x7C
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#define BMI088_ACCEL_REG_INT_MAP_DATA 0x58
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#define BMI088_ACCEL_INT_MAP_DATA_BIT_INT1_DRDY BIT(2)
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#define BMI088_ACCEL_INT_MAP_DATA_BIT_INT2_FWM BIT(5)
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#define BMI088_ACCEL_REG_INT1_IO_CONF 0x53
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#define BMI088_ACCEL_INT1_IO_CONF_BIT_ENABLE_OUT BIT(3)
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#define BMI088_ACCEL_INT1_IO_CONF_BIT_LVL BIT(1)
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#define BMI088_ACCEL_REG_INT2_IO_CONF 0x54
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#define BMI088_ACCEL_INT2_IO_CONF_BIT_ENABLE_OUT BIT(3)
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#define BMI088_ACCEL_INT2_IO_CONF_BIT_LVL BIT(1)
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#define BMI088_ACCEL_REG_ACC_CONF 0x40
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#define BMI088_ACCEL_MODE_ODR_MASK 0x0f
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#define BMI088_ACCEL_REG_ACC_RANGE 0x41
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#define BMI088_ACCEL_RANGE_3G 0x00
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#define BMI088_ACCEL_RANGE_6G 0x01
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#define BMI088_ACCEL_RANGE_12G 0x02
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#define BMI088_ACCEL_RANGE_24G 0x03
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#define BMI088_ACCEL_REG_TEMP 0x22
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#define BMI088_ACCEL_REG_TEMP_SHIFT 5
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#define BMI088_ACCEL_TEMP_UNIT 125
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#define BMI088_ACCEL_TEMP_OFFSET 23000
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#define BMI088_ACCEL_REG_XOUT_L 0x12
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#define BMI088_ACCEL_AXIS_TO_REG(axis) \
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(BMI088_ACCEL_REG_XOUT_L + (axis * 2))
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#define BMI088_ACCEL_MAX_STARTUP_TIME_US 1000
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#define BMI088_AUTO_SUSPEND_DELAY_MS 2000
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#define BMI088_ACCEL_REG_FIFO_STATUS 0x0E
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#define BMI088_ACCEL_REG_FIFO_CONFIG0 0x48
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#define BMI088_ACCEL_REG_FIFO_CONFIG1 0x49
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#define BMI088_ACCEL_REG_FIFO_DATA 0x3F
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#define BMI088_ACCEL_FIFO_LENGTH 100
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#define BMI088_ACCEL_FIFO_MODE_FIFO 0x40
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#define BMI088_ACCEL_FIFO_MODE_STREAM 0x80
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#define BMIO088_ACCEL_ACC_RANGE_MSK GENMASK(1, 0)
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enum bmi088_accel_axis {
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AXIS_X,
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AXIS_Y,
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AXIS_Z,
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};
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static const int bmi088_sample_freqs[] = {
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12, 500000,
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25, 0,
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50, 0,
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100, 0,
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200, 0,
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400, 0,
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800, 0,
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1600, 0,
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};
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/* Available OSR (over sampling rate) sets the 3dB cut-off frequency */
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enum bmi088_osr_modes {
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BMI088_ACCEL_MODE_OSR_NORMAL = 0xA,
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BMI088_ACCEL_MODE_OSR_2 = 0x9,
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BMI088_ACCEL_MODE_OSR_4 = 0x8,
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};
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/* Available ODR (output data rates) in Hz */
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enum bmi088_odr_modes {
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BMI088_ACCEL_MODE_ODR_12_5 = 0x5,
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BMI088_ACCEL_MODE_ODR_25 = 0x6,
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BMI088_ACCEL_MODE_ODR_50 = 0x7,
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BMI088_ACCEL_MODE_ODR_100 = 0x8,
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BMI088_ACCEL_MODE_ODR_200 = 0x9,
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BMI088_ACCEL_MODE_ODR_400 = 0xa,
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BMI088_ACCEL_MODE_ODR_800 = 0xb,
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BMI088_ACCEL_MODE_ODR_1600 = 0xc,
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};
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struct bmi088_scale_info {
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int scale;
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u8 reg_range;
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};
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struct bmi088_accel_chip_info {
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const char *name;
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u8 chip_id;
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const struct iio_chan_spec *channels;
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int num_channels;
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const int scale_table[4][2];
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};
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struct bmi088_accel_data {
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struct regmap *regmap;
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const struct bmi088_accel_chip_info *chip_info;
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u8 buffer[2] __aligned(IIO_DMA_MINALIGN); /* shared DMA safe buffer */
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};
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static const struct regmap_range bmi088_volatile_ranges[] = {
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/* All registers below 0x40 are volatile, except the CHIP ID. */
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regmap_reg_range(BMI088_ACCEL_REG_ERROR, 0x3f),
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/* Mark the RESET as volatile too, it is self-clearing */
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regmap_reg_range(BMI088_ACCEL_REG_RESET, BMI088_ACCEL_REG_RESET),
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};
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static const struct regmap_access_table bmi088_volatile_table = {
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.yes_ranges = bmi088_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(bmi088_volatile_ranges),
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};
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const struct regmap_config bmi088_regmap_conf = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = 0x7E,
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.volatile_table = &bmi088_volatile_table,
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.cache_type = REGCACHE_RBTREE,
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};
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EXPORT_SYMBOL_NS_GPL(bmi088_regmap_conf, IIO_BMI088);
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static int bmi088_accel_power_up(struct bmi088_accel_data *data)
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{
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int ret;
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/* Enable accelerometer and temperature sensor */
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ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x4);
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if (ret)
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return ret;
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/* Datasheet recommends to wait at least 5ms before communication */
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usleep_range(5000, 6000);
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/* Disable suspend mode */
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ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x0);
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if (ret)
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return ret;
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/* Recommended at least 1ms before further communication */
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usleep_range(1000, 1200);
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return 0;
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}
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static int bmi088_accel_power_down(struct bmi088_accel_data *data)
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{
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int ret;
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/* Enable suspend mode */
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ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x3);
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if (ret)
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return ret;
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/* Recommended at least 1ms before further communication */
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usleep_range(1000, 1200);
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/* Disable accelerometer and temperature sensor */
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ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x0);
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if (ret)
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return ret;
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/* Datasheet recommends to wait at least 5ms before communication */
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usleep_range(5000, 6000);
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return 0;
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}
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static int bmi088_accel_get_sample_freq(struct bmi088_accel_data *data,
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int *val, int *val2)
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{
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unsigned int value;
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int ret;
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ret = regmap_read(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
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&value);
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if (ret)
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return ret;
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value &= BMI088_ACCEL_MODE_ODR_MASK;
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value -= BMI088_ACCEL_MODE_ODR_12_5;
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value <<= 1;
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if (value >= ARRAY_SIZE(bmi088_sample_freqs) - 1)
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return -EINVAL;
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*val = bmi088_sample_freqs[value];
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*val2 = bmi088_sample_freqs[value + 1];
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return IIO_VAL_INT_PLUS_MICRO;
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}
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static int bmi088_accel_set_sample_freq(struct bmi088_accel_data *data, int val)
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{
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unsigned int regval;
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int index = 0;
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while (index < ARRAY_SIZE(bmi088_sample_freqs) &&
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bmi088_sample_freqs[index] != val)
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index += 2;
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if (index >= ARRAY_SIZE(bmi088_sample_freqs))
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return -EINVAL;
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regval = (index >> 1) + BMI088_ACCEL_MODE_ODR_12_5;
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return regmap_update_bits(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
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BMI088_ACCEL_MODE_ODR_MASK, regval);
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}
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static int bmi088_accel_set_scale(struct bmi088_accel_data *data, int val, int val2)
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{
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unsigned int i;
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for (i = 0; i < 4; i++)
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if (val == data->chip_info->scale_table[i][0] &&
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val2 == data->chip_info->scale_table[i][1])
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break;
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if (i == 4)
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return -EINVAL;
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return regmap_write(data->regmap, BMI088_ACCEL_REG_ACC_RANGE, i);
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}
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static int bmi088_accel_get_temp(struct bmi088_accel_data *data, int *val)
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{
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int ret;
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s16 temp;
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ret = regmap_bulk_read(data->regmap, BMI088_ACCEL_REG_TEMP,
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&data->buffer, sizeof(__be16));
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if (ret)
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return ret;
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/* data->buffer is cacheline aligned */
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temp = be16_to_cpu(*(__be16 *)data->buffer);
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*val = temp >> BMI088_ACCEL_REG_TEMP_SHIFT;
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return IIO_VAL_INT;
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}
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static int bmi088_accel_get_axis(struct bmi088_accel_data *data,
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struct iio_chan_spec const *chan,
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int *val)
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{
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int ret;
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s16 raw_val;
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ret = regmap_bulk_read(data->regmap,
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BMI088_ACCEL_AXIS_TO_REG(chan->scan_index),
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data->buffer, sizeof(__le16));
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if (ret)
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return ret;
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raw_val = le16_to_cpu(*(__le16 *)data->buffer);
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*val = raw_val;
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return IIO_VAL_INT;
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}
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static int bmi088_accel_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct bmi088_accel_data *data = iio_priv(indio_dev);
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struct device *dev = regmap_get_device(data->regmap);
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int ret;
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int reg;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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switch (chan->type) {
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case IIO_TEMP:
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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ret = bmi088_accel_get_temp(data, val);
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goto out_read_raw_pm_put;
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case IIO_ACCEL:
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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ret = iio_device_claim_direct_mode(indio_dev);
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if (ret)
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goto out_read_raw_pm_put;
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ret = bmi088_accel_get_axis(data, chan, val);
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iio_device_release_direct_mode(indio_dev);
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if (!ret)
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ret = IIO_VAL_INT;
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goto out_read_raw_pm_put;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_OFFSET:
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switch (chan->type) {
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case IIO_TEMP:
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/* Offset applies before scale */
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*val = BMI088_ACCEL_TEMP_OFFSET/BMI088_ACCEL_TEMP_UNIT;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_SCALE:
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switch (chan->type) {
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case IIO_TEMP:
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/* 0.125 degrees per LSB */
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*val = BMI088_ACCEL_TEMP_UNIT;
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return IIO_VAL_INT;
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case IIO_ACCEL:
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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ret = regmap_read(data->regmap,
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BMI088_ACCEL_REG_ACC_RANGE, ®);
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if (ret)
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goto out_read_raw_pm_put;
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reg = FIELD_GET(BMIO088_ACCEL_ACC_RANGE_MSK, reg);
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*val = data->chip_info->scale_table[reg][0];
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*val2 = data->chip_info->scale_table[reg][1];
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ret = IIO_VAL_INT_PLUS_MICRO;
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goto out_read_raw_pm_put;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_SAMP_FREQ:
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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ret = bmi088_accel_get_sample_freq(data, val, val2);
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goto out_read_raw_pm_put;
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default:
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break;
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}
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return -EINVAL;
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out_read_raw_pm_put:
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return ret;
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}
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static int bmi088_accel_read_avail(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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const int **vals, int *type, int *length,
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long mask)
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{
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struct bmi088_accel_data *data = iio_priv(indio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_SCALE:
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*vals = (const int *)data->chip_info->scale_table;
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*length = 8;
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*type = IIO_VAL_INT_PLUS_MICRO;
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return IIO_AVAIL_LIST;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*type = IIO_VAL_INT_PLUS_MICRO;
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*vals = bmi088_sample_freqs;
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*length = ARRAY_SIZE(bmi088_sample_freqs);
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return IIO_AVAIL_LIST;
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default:
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return -EINVAL;
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}
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}
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static int bmi088_accel_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct bmi088_accel_data *data = iio_priv(indio_dev);
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struct device *dev = regmap_get_device(data->regmap);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_SCALE:
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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ret = bmi088_accel_set_scale(data, val, val2);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return ret;
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case IIO_CHAN_INFO_SAMP_FREQ:
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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ret = bmi088_accel_set_sample_freq(data, val);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return ret;
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default:
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return -EINVAL;
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}
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}
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#define BMI088_ACCEL_CHANNEL(_axis) { \
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.type = IIO_ACCEL, \
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.modified = 1, \
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.channel2 = IIO_MOD_##_axis, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = AXIS_##_axis, \
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}
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static const struct iio_chan_spec bmi088_accel_channels[] = {
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{
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.type = IIO_TEMP,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE) |
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BIT(IIO_CHAN_INFO_OFFSET),
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.scan_index = -1,
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},
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BMI088_ACCEL_CHANNEL(X),
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BMI088_ACCEL_CHANNEL(Y),
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BMI088_ACCEL_CHANNEL(Z),
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IIO_CHAN_SOFT_TIMESTAMP(3),
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};
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static const struct bmi088_accel_chip_info bmi088_accel_chip_info_tbl[] = {
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[BOSCH_BMI085] = {
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.name = "bmi085-accel",
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.chip_id = 0x1F,
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.channels = bmi088_accel_channels,
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.num_channels = ARRAY_SIZE(bmi088_accel_channels),
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.scale_table = {{0, 598}, {0, 1196}, {0, 2393}, {0, 4785}},
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},
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[BOSCH_BMI088] = {
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.name = "bmi088-accel",
|
|
.chip_id = 0x1E,
|
|
.channels = bmi088_accel_channels,
|
|
.num_channels = ARRAY_SIZE(bmi088_accel_channels),
|
|
.scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
|
|
},
|
|
[BOSCH_BMI090L] = {
|
|
.name = "bmi090l-accel",
|
|
.chip_id = 0x1A,
|
|
.channels = bmi088_accel_channels,
|
|
.num_channels = ARRAY_SIZE(bmi088_accel_channels),
|
|
.scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
|
|
},
|
|
};
|
|
|
|
static const struct iio_info bmi088_accel_info = {
|
|
.read_raw = bmi088_accel_read_raw,
|
|
.write_raw = bmi088_accel_write_raw,
|
|
.read_avail = bmi088_accel_read_avail,
|
|
};
|
|
|
|
static const unsigned long bmi088_accel_scan_masks[] = {
|
|
BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
|
|
0
|
|
};
|
|
|
|
static int bmi088_accel_chip_init(struct bmi088_accel_data *data, enum bmi_device_type type)
|
|
{
|
|
struct device *dev = regmap_get_device(data->regmap);
|
|
int ret, i;
|
|
unsigned int val;
|
|
|
|
if (type >= BOSCH_UNKNOWN)
|
|
return -ENODEV;
|
|
|
|
/* Do a dummy read to enable SPI interface, won't harm I2C */
|
|
regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
|
|
|
|
/*
|
|
* Reset chip to get it in a known good state. A delay of 1ms after
|
|
* reset is required according to the data sheet
|
|
*/
|
|
ret = regmap_write(data->regmap, BMI088_ACCEL_REG_RESET,
|
|
BMI088_ACCEL_RESET_VAL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
/* Do a dummy read again after a reset to enable the SPI interface */
|
|
regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
|
|
|
|
/* Read chip ID */
|
|
ret = regmap_read(data->regmap, BMI088_ACCEL_REG_CHIP_ID, &val);
|
|
if (ret) {
|
|
dev_err(dev, "Error: Reading chip id\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Validate chip ID */
|
|
for (i = 0; i < ARRAY_SIZE(bmi088_accel_chip_info_tbl); i++)
|
|
if (bmi088_accel_chip_info_tbl[i].chip_id == val)
|
|
break;
|
|
|
|
if (i == ARRAY_SIZE(bmi088_accel_chip_info_tbl))
|
|
data->chip_info = &bmi088_accel_chip_info_tbl[type];
|
|
else
|
|
data->chip_info = &bmi088_accel_chip_info_tbl[i];
|
|
|
|
if (i != type)
|
|
dev_warn(dev, "unexpected chip id 0x%X\n", val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap,
|
|
int irq, enum bmi_device_type type)
|
|
{
|
|
struct bmi088_accel_data *data;
|
|
struct iio_dev *indio_dev;
|
|
int ret;
|
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
data = iio_priv(indio_dev);
|
|
dev_set_drvdata(dev, indio_dev);
|
|
|
|
data->regmap = regmap;
|
|
|
|
ret = bmi088_accel_chip_init(data, type);
|
|
if (ret)
|
|
return ret;
|
|
|
|
indio_dev->channels = data->chip_info->channels;
|
|
indio_dev->num_channels = data->chip_info->num_channels;
|
|
indio_dev->name = data->chip_info->name;
|
|
indio_dev->available_scan_masks = bmi088_accel_scan_masks;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->info = &bmi088_accel_info;
|
|
|
|
/* Enable runtime PM */
|
|
pm_runtime_get_noresume(dev);
|
|
pm_runtime_set_suspended(dev);
|
|
pm_runtime_enable(dev);
|
|
/* We need ~6ms to startup, so set the delay to 6 seconds */
|
|
pm_runtime_set_autosuspend_delay(dev, 6000);
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_put(dev);
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret)
|
|
dev_err(dev, "Unable to register iio device\n");
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_probe, IIO_BMI088);
|
|
|
|
|
|
void bmi088_accel_core_remove(struct device *dev)
|
|
{
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
|
struct bmi088_accel_data *data = iio_priv(indio_dev);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_suspended(dev);
|
|
bmi088_accel_power_down(data);
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_remove, IIO_BMI088);
|
|
|
|
static int bmi088_accel_runtime_suspend(struct device *dev)
|
|
{
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
|
struct bmi088_accel_data *data = iio_priv(indio_dev);
|
|
|
|
return bmi088_accel_power_down(data);
|
|
}
|
|
|
|
static int bmi088_accel_runtime_resume(struct device *dev)
|
|
{
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
|
struct bmi088_accel_data *data = iio_priv(indio_dev);
|
|
|
|
return bmi088_accel_power_up(data);
|
|
}
|
|
|
|
EXPORT_NS_GPL_RUNTIME_DEV_PM_OPS(bmi088_accel_pm_ops,
|
|
bmi088_accel_runtime_suspend,
|
|
bmi088_accel_runtime_resume, NULL,
|
|
IIO_BMI088);
|
|
|
|
MODULE_AUTHOR("Niek van Agt <niek.van.agt@topicproducts.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("BMI088 accelerometer driver (core)");
|