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![Jonathan Cameron](/assets/img/avatar_default.png)
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes tag is probably not where the issue was first introduced, but
is likely to be far beyond the point where anyone considers
backporting this fix.
Fixes: 58f08b0af8
("staging:iio:resolver:ad2s90 general cleanup")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-90-jic23@kernel.org
130 lines
3 KiB
C
130 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ad2s90.c simple support for the ADI Resolver to Digital Converters: AD2S90
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*
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* Copyright (c) 2010-2010 Analog Devices Inc.
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*/
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#include <linux/types.h>
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#include <linux/mutex.h>
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#include <linux/device.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/module.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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/*
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* Although chip's max frequency is 2Mhz, it needs 600ns between CS and the
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* first falling edge of SCLK, so frequency should be at most 1 / (2 * 6e-7)
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*/
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#define AD2S90_MAX_SPI_FREQ_HZ 830000
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struct ad2s90_state {
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struct mutex lock; /* lock to protect rx buffer */
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struct spi_device *sdev;
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u8 rx[2] __aligned(IIO_DMA_MINALIGN);
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};
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static int ad2s90_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long m)
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{
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int ret;
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struct ad2s90_state *st = iio_priv(indio_dev);
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if (chan->type != IIO_ANGL)
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return -EINVAL;
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switch (m) {
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case IIO_CHAN_INFO_SCALE:
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/* 2 * Pi / 2^12 */
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*val = 6283; /* mV */
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*val2 = 12;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&st->lock);
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ret = spi_read(st->sdev, st->rx, 2);
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if (ret < 0) {
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mutex_unlock(&st->lock);
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return ret;
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}
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*val = (((u16)(st->rx[0])) << 4) | ((st->rx[1] & 0xF0) >> 4);
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mutex_unlock(&st->lock);
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return IIO_VAL_INT;
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default:
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break;
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}
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return -EINVAL;
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}
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static const struct iio_info ad2s90_info = {
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.read_raw = ad2s90_read_raw,
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};
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static const struct iio_chan_spec ad2s90_chan = {
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.type = IIO_ANGL,
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.indexed = 1,
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.channel = 0,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
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};
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static int ad2s90_probe(struct spi_device *spi)
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{
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struct iio_dev *indio_dev;
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struct ad2s90_state *st;
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if (spi->max_speed_hz > AD2S90_MAX_SPI_FREQ_HZ) {
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dev_err(&spi->dev, "SPI CLK, %d Hz exceeds %d Hz\n",
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spi->max_speed_hz, AD2S90_MAX_SPI_FREQ_HZ);
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return -EINVAL;
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}
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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if (!indio_dev)
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return -ENOMEM;
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st = iio_priv(indio_dev);
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spi_set_drvdata(spi, indio_dev);
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mutex_init(&st->lock);
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st->sdev = spi;
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indio_dev->info = &ad2s90_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = &ad2s90_chan;
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indio_dev->num_channels = 1;
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indio_dev->name = spi_get_device_id(spi)->name;
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return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
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}
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static const struct of_device_id ad2s90_of_match[] = {
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{ .compatible = "adi,ad2s90", },
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{}
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};
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MODULE_DEVICE_TABLE(of, ad2s90_of_match);
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static const struct spi_device_id ad2s90_id[] = {
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{ "ad2s90" },
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{}
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};
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MODULE_DEVICE_TABLE(spi, ad2s90_id);
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static struct spi_driver ad2s90_driver = {
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.driver = {
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.name = "ad2s90",
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.of_match_table = ad2s90_of_match,
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},
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.probe = ad2s90_probe,
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.id_table = ad2s90_id,
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};
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module_spi_driver(ad2s90_driver);
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MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
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MODULE_DESCRIPTION("Analog Devices AD2S90 Resolver to Digital SPI driver");
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MODULE_LICENSE("GPL v2");
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