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44377f622e
The defines and typedefs (hw_interrupt_type, no_irq_type, irq_desc_t) have been kept around for migration reasons. After more than two years it's time to remove them finally. This patch cleans up one of the remaining users. When all such patches hit mainline we can remove the defines and typedefs finally. Impact: cleanup Convert the last remaining users to struct irq_chip and remove the define. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
652 lines
17 KiB
C
652 lines
17 KiB
C
/*
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* linux/arch/alpha/kernel/sys_sable.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Code supporting the Sable, Sable-Gamma, and Lynx systems.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_t2.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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DEFINE_SPINLOCK(sable_lynx_irq_lock);
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typedef struct irq_swizzle_struct
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{
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char irq_to_mask[64];
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char mask_to_irq[64];
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/* Note mask bit is true for DISABLED irqs. */
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unsigned long shadow_mask;
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void (*update_irq_hw)(unsigned long bit, unsigned long mask);
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void (*ack_irq_hw)(unsigned long bit);
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} irq_swizzle_t;
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static irq_swizzle_t *sable_lynx_irq_swizzle;
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static void sable_lynx_init_irq(int nr_of_irqs);
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
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/***********************************************************************/
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/*
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* For SABLE, which is really baroque, we manage 40 IRQ's, but the
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* hardware really only supports 24, not via normal ISA PIC,
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* but cascaded custom 8259's, etc.
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* 0-7 (char at 536)
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* 8-15 (char at 53a)
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* 16-23 (char at 53c)
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*
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* Summary Registers (536/53a/53c):
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*
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* Bit Meaning Kernel IRQ
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*------------------------------------------
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* 0 PCI slot 0 34
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* 1 NCR810 (builtin) 33
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* 2 TULIP (builtin) 32
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* 3 mouse 12
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* 4 PCI slot 1 35
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* 5 PCI slot 2 36
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* 6 keyboard 1
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* 7 floppy 6
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* 8 COM2 3
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* 9 parallel port 7
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*10 EISA irq 3 -
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*11 EISA irq 4 -
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*12 EISA irq 5 5
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*13 EISA irq 6 -
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*14 EISA irq 7 -
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*15 COM1 4
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*16 EISA irq 9 9
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*17 EISA irq 10 10
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*18 EISA irq 11 11
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*19 EISA irq 12 -
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*20 EISA irq 13 -
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*21 EISA irq 14 14
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*22 NC 15
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*23 IIC -
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*/
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static void
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sable_update_irq_hw(unsigned long bit, unsigned long mask)
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{
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int port = 0x537;
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if (bit >= 16) {
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port = 0x53d;
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mask >>= 16;
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} else if (bit >= 8) {
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port = 0x53b;
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mask >>= 8;
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}
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outb(mask, port);
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}
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static void
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sable_ack_irq_hw(unsigned long bit)
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{
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int port, val1, val2;
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if (bit >= 16) {
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port = 0x53c;
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val1 = 0xE0 | (bit - 16);
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val2 = 0xE0 | 4;
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} else if (bit >= 8) {
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port = 0x53a;
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val1 = 0xE0 | (bit - 8);
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val2 = 0xE0 | 3;
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} else {
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port = 0x536;
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val1 = 0xE0 | (bit - 0);
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val2 = 0xE0 | 1;
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}
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outb(val1, port); /* ack the slave */
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outb(val2, 0x534); /* ack the master */
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}
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static irq_swizzle_t sable_irq_swizzle = {
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{
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-1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
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-1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 0-7 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 8-15 */
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2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
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-1, -1, -1, -1, -1, -1, -1, -1, /* */
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-1, -1, -1, -1, -1, -1, -1, -1, /* */
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-1, -1, -1, -1, -1, -1, -1, -1 /* */
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},
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{
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34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */
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3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
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9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* */
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-1, -1, -1, -1, -1, -1, -1, -1, /* */
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-1, -1, -1, -1, -1, -1, -1, -1, /* */
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-1, -1, -1, -1, -1, -1, -1, -1, /* */
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-1, -1, -1, -1, -1, -1, -1, -1 /* */
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},
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-1,
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sable_update_irq_hw,
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sable_ack_irq_hw
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};
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static void __init
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sable_init_irq(void)
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{
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outb(-1, 0x537); /* slave 0 */
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outb(-1, 0x53b); /* slave 1 */
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outb(-1, 0x53d); /* slave 2 */
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outb(0x44, 0x535); /* enable cascades in master */
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sable_lynx_irq_swizzle = &sable_irq_swizzle;
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sable_lynx_init_irq(40);
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}
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/*
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* PCI Fixup configuration for ALPHA SABLE (2100).
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*
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* The device to slot mapping looks like:
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*
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* Slot Device
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* 0 TULIP
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* 1 SCSI
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* 2 PCI-EISA bridge
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* 3 none
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* 4 none
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* 5 none
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* 6 PCI on board slot 0
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* 7 PCI on board slot 1
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* 8 PCI on board slot 2
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*
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*
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* This two layered interrupt approach means that we allocate IRQ 16 and
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* above for PCI interrupts. The IRQ relates to which bit the interrupt
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* comes in on. This makes interrupt processing much easier.
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*/
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/*
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* NOTE: the IRQ assignments below are arbitrary, but need to be consistent
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* with the values in the irq swizzling tables above.
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*/
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static int __init
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sable_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[9][5] __initdata = {
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/*INT INTA INTB INTC INTD */
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{ 32+0, 32+0, 32+0, 32+0, 32+0}, /* IdSel 0, TULIP */
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{ 32+1, 32+1, 32+1, 32+1, 32+1}, /* IdSel 1, SCSI */
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{ -1, -1, -1, -1, -1}, /* IdSel 2, SIO */
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{ -1, -1, -1, -1, -1}, /* IdSel 3, none */
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{ -1, -1, -1, -1, -1}, /* IdSel 4, none */
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{ -1, -1, -1, -1, -1}, /* IdSel 5, none */
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{ 32+2, 32+2, 32+2, 32+2, 32+2}, /* IdSel 6, slot 0 */
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{ 32+3, 32+3, 32+3, 32+3, 32+3}, /* IdSel 7, slot 1 */
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{ 32+4, 32+4, 32+4, 32+4, 32+4} /* IdSel 8, slot 2 */
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};
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long min_idsel = 0, max_idsel = 8, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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#endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
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/***********************************************************************/
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/* LYNX hardware specifics
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*/
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/*
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* For LYNX, which is also baroque, we manage 64 IRQs, via a custom IC.
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*
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* Bit Meaning Kernel IRQ
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*------------------------------------------
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* 0
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* 1
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* 2
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* 3 mouse 12
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* 4
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* 5
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* 6 keyboard 1
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* 7 floppy 6
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* 8 COM2 3
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* 9 parallel port 7
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*10 EISA irq 3 -
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*11 EISA irq 4 -
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*12 EISA irq 5 5
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*13 EISA irq 6 -
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*14 EISA irq 7 -
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*15 COM1 4
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*16 EISA irq 9 9
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*17 EISA irq 10 10
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*18 EISA irq 11 11
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*19 EISA irq 12 -
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*20
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*21 EISA irq 14 14
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*22 EISA irq 15 15
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*23 IIC -
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*24 VGA (builtin) -
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*25
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*26
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*27
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*28 NCR810 (builtin) 28
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*29
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*30
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*31
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*32 PCI 0 slot 4 A primary bus 32
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*33 PCI 0 slot 4 B primary bus 33
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*34 PCI 0 slot 4 C primary bus 34
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*35 PCI 0 slot 4 D primary bus
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*36 PCI 0 slot 5 A primary bus
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*37 PCI 0 slot 5 B primary bus
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*38 PCI 0 slot 5 C primary bus
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*39 PCI 0 slot 5 D primary bus
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*40 PCI 0 slot 6 A primary bus
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*41 PCI 0 slot 6 B primary bus
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*42 PCI 0 slot 6 C primary bus
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*43 PCI 0 slot 6 D primary bus
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*44 PCI 0 slot 7 A primary bus
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*45 PCI 0 slot 7 B primary bus
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*46 PCI 0 slot 7 C primary bus
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*47 PCI 0 slot 7 D primary bus
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*48 PCI 0 slot 0 A secondary bus
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*49 PCI 0 slot 0 B secondary bus
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*50 PCI 0 slot 0 C secondary bus
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*51 PCI 0 slot 0 D secondary bus
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*52 PCI 0 slot 1 A secondary bus
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*53 PCI 0 slot 1 B secondary bus
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*54 PCI 0 slot 1 C secondary bus
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*55 PCI 0 slot 1 D secondary bus
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*56 PCI 0 slot 2 A secondary bus
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*57 PCI 0 slot 2 B secondary bus
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*58 PCI 0 slot 2 C secondary bus
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*59 PCI 0 slot 2 D secondary bus
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*60 PCI 0 slot 3 A secondary bus
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*61 PCI 0 slot 3 B secondary bus
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*62 PCI 0 slot 3 C secondary bus
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*63 PCI 0 slot 3 D secondary bus
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*/
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static void
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lynx_update_irq_hw(unsigned long bit, unsigned long mask)
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{
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/*
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* Write the AIR register on the T3/T4 with the
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* address of the IC mask register (offset 0x40)
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*/
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*(vulp)T2_AIR = 0x40;
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mb();
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*(vulp)T2_AIR; /* re-read to force write */
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mb();
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*(vulp)T2_DIR = mask;
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mb();
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mb();
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}
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static void
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lynx_ack_irq_hw(unsigned long bit)
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{
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*(vulp)T2_VAR = (u_long) bit;
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mb();
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mb();
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}
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static irq_swizzle_t lynx_irq_swizzle = {
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{ /* irq_to_mask */
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-1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
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-1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* pseudo */
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-1, -1, -1, -1, 28, -1, -1, -1, /* pseudo */
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32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
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40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
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48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
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56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
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},
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{ /* mask_to_irq */
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-1, -1, -1, 12, -1, -1, 1, 6, /* mask 0-7 */
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3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
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9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
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-1, -1, -1, -1, 28, -1, -1, -1, /* mask 24-31 */
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32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
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40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
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48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
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56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
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},
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-1,
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lynx_update_irq_hw,
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lynx_ack_irq_hw
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};
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static void __init
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lynx_init_irq(void)
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{
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sable_lynx_irq_swizzle = &lynx_irq_swizzle;
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sable_lynx_init_irq(64);
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}
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/*
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* PCI Fixup configuration for ALPHA LYNX (2100A)
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*
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* The device to slot mapping looks like:
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*
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* Slot Device
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* 0 none
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* 1 none
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* 2 PCI-EISA bridge
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* 3 PCI-PCI bridge
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* 4 NCR 810 (Demi-Lynx only)
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* 5 none
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* 6 PCI on board slot 4
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* 7 PCI on board slot 5
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* 8 PCI on board slot 6
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* 9 PCI on board slot 7
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*
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* And behind the PPB we have:
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*
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* 11 PCI on board slot 0
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* 12 PCI on board slot 1
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* 13 PCI on board slot 2
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* 14 PCI on board slot 3
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*/
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/*
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* NOTE: the IRQ assignments below are arbitrary, but need to be consistent
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* with the values in the irq swizzling tables above.
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*/
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static int __init
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lynx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[19][5] __initdata = {
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/*INT INTA INTB INTC INTD */
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{ -1, -1, -1, -1, -1}, /* IdSel 13, PCEB */
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{ -1, -1, -1, -1, -1}, /* IdSel 14, PPB */
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{ 28, 28, 28, 28, 28}, /* IdSel 15, NCR demi */
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{ -1, -1, -1, -1, -1}, /* IdSel 16, none */
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{ 32, 32, 33, 34, 35}, /* IdSel 17, slot 4 */
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{ 36, 36, 37, 38, 39}, /* IdSel 18, slot 5 */
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{ 40, 40, 41, 42, 43}, /* IdSel 19, slot 6 */
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{ 44, 44, 45, 46, 47}, /* IdSel 20, slot 7 */
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{ -1, -1, -1, -1, -1}, /* IdSel 22, none */
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/* The following are actually behind the PPB. */
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{ -1, -1, -1, -1, -1}, /* IdSel 16 none */
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{ 28, 28, 28, 28, 28}, /* IdSel 17 NCR lynx */
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{ -1, -1, -1, -1, -1}, /* IdSel 18 none */
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{ -1, -1, -1, -1, -1}, /* IdSel 19 none */
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{ -1, -1, -1, -1, -1}, /* IdSel 20 none */
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{ -1, -1, -1, -1, -1}, /* IdSel 21 none */
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{ 48, 48, 49, 50, 51}, /* IdSel 22 slot 0 */
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{ 52, 52, 53, 54, 55}, /* IdSel 23 slot 1 */
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{ 56, 56, 57, 58, 59}, /* IdSel 24 slot 2 */
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{ 60, 60, 61, 62, 63} /* IdSel 25 slot 3 */
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};
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const long min_idsel = 2, max_idsel = 20, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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static u8 __init
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lynx_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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int slot, pin = *pinp;
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if (dev->bus->number == 0) {
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slot = PCI_SLOT(dev->devfn);
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}
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/* Check for the built-in bridge */
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else if (PCI_SLOT(dev->bus->self->devfn) == 3) {
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slot = PCI_SLOT(dev->devfn) + 11;
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}
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else
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{
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/* Must be a card-based bridge. */
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do {
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if (PCI_SLOT(dev->bus->self->devfn) == 3) {
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slot = PCI_SLOT(dev->devfn) + 11;
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break;
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}
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pin = pci_swizzle_interrupt_pin(dev, pin);
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/* Move up the chain of bridges. */
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dev = dev->bus->self;
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/* Slot of the next bridge. */
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slot = PCI_SLOT(dev->devfn);
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} while (dev->bus->self);
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}
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*pinp = pin;
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return slot;
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}
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#endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) */
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/***********************************************************************/
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/* GENERIC irq routines */
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static inline void
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sable_lynx_enable_irq(unsigned int irq)
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{
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unsigned long bit, mask;
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bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
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spin_lock(&sable_lynx_irq_lock);
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mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
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sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
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spin_unlock(&sable_lynx_irq_lock);
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#if 0
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printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
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__func__, mask, bit, irq);
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#endif
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}
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static void
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sable_lynx_disable_irq(unsigned int irq)
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{
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unsigned long bit, mask;
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bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
|
spin_lock(&sable_lynx_irq_lock);
|
|
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
|
|
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
|
spin_unlock(&sable_lynx_irq_lock);
|
|
#if 0
|
|
printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
|
|
__func__, mask, bit, irq);
|
|
#endif
|
|
}
|
|
|
|
static unsigned int
|
|
sable_lynx_startup_irq(unsigned int irq)
|
|
{
|
|
sable_lynx_enable_irq(irq);
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
sable_lynx_end_irq(unsigned int irq)
|
|
{
|
|
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
sable_lynx_enable_irq(irq);
|
|
}
|
|
|
|
static void
|
|
sable_lynx_mask_and_ack_irq(unsigned int irq)
|
|
{
|
|
unsigned long bit, mask;
|
|
|
|
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
|
spin_lock(&sable_lynx_irq_lock);
|
|
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
|
|
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
|
sable_lynx_irq_swizzle->ack_irq_hw(bit);
|
|
spin_unlock(&sable_lynx_irq_lock);
|
|
}
|
|
|
|
static struct irq_chip sable_lynx_irq_type = {
|
|
.typename = "SABLE/LYNX",
|
|
.startup = sable_lynx_startup_irq,
|
|
.shutdown = sable_lynx_disable_irq,
|
|
.enable = sable_lynx_enable_irq,
|
|
.disable = sable_lynx_disable_irq,
|
|
.ack = sable_lynx_mask_and_ack_irq,
|
|
.end = sable_lynx_end_irq,
|
|
};
|
|
|
|
static void
|
|
sable_lynx_srm_device_interrupt(unsigned long vector)
|
|
{
|
|
/* Note that the vector reported by the SRM PALcode corresponds
|
|
to the interrupt mask bits, but we have to manage via the
|
|
so-called legacy IRQs for many common devices. */
|
|
|
|
int bit, irq;
|
|
|
|
bit = (vector - 0x800) >> 4;
|
|
irq = sable_lynx_irq_swizzle->mask_to_irq[bit];
|
|
#if 0
|
|
printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n",
|
|
__func__, vector, bit, irq);
|
|
#endif
|
|
handle_irq(irq);
|
|
}
|
|
|
|
static void __init
|
|
sable_lynx_init_irq(int nr_of_irqs)
|
|
{
|
|
long i;
|
|
|
|
for (i = 0; i < nr_of_irqs; ++i) {
|
|
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
|
|
irq_desc[i].chip = &sable_lynx_irq_type;
|
|
}
|
|
|
|
common_init_isa_dma();
|
|
}
|
|
|
|
static void __init
|
|
sable_lynx_init_pci(void)
|
|
{
|
|
common_init_pci();
|
|
}
|
|
|
|
/*****************************************************************/
|
|
/*
|
|
* The System Vectors
|
|
*
|
|
* In order that T2_HAE_ADDRESS should be a constant, we play
|
|
* these games with GAMMA_BIAS.
|
|
*/
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || \
|
|
(defined(CONFIG_ALPHA_SABLE) && !defined(CONFIG_ALPHA_GAMMA))
|
|
#undef GAMMA_BIAS
|
|
#define GAMMA_BIAS 0
|
|
struct alpha_machine_vector sable_mv __initmv = {
|
|
.vector_name = "Sable",
|
|
DO_EV4_MMU,
|
|
DO_DEFAULT_RTC,
|
|
DO_T2_IO,
|
|
.machine_check = t2_machine_check,
|
|
.max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
|
|
.min_io_address = EISA_DEFAULT_IO_BASE,
|
|
.min_mem_address = T2_DEFAULT_MEM_BASE,
|
|
|
|
.nr_irqs = 40,
|
|
.device_interrupt = sable_lynx_srm_device_interrupt,
|
|
|
|
.init_arch = t2_init_arch,
|
|
.init_irq = sable_init_irq,
|
|
.init_rtc = common_init_rtc,
|
|
.init_pci = sable_lynx_init_pci,
|
|
.kill_arch = t2_kill_arch,
|
|
.pci_map_irq = sable_map_irq,
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
.sys = { .t2 = {
|
|
.gamma_bias = 0
|
|
} }
|
|
};
|
|
ALIAS_MV(sable)
|
|
#endif /* GENERIC || (SABLE && !GAMMA) */
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || \
|
|
(defined(CONFIG_ALPHA_SABLE) && defined(CONFIG_ALPHA_GAMMA))
|
|
#undef GAMMA_BIAS
|
|
#define GAMMA_BIAS _GAMMA_BIAS
|
|
struct alpha_machine_vector sable_gamma_mv __initmv = {
|
|
.vector_name = "Sable-Gamma",
|
|
DO_EV5_MMU,
|
|
DO_DEFAULT_RTC,
|
|
DO_T2_IO,
|
|
.machine_check = t2_machine_check,
|
|
.max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
|
|
.min_io_address = EISA_DEFAULT_IO_BASE,
|
|
.min_mem_address = T2_DEFAULT_MEM_BASE,
|
|
|
|
.nr_irqs = 40,
|
|
.device_interrupt = sable_lynx_srm_device_interrupt,
|
|
|
|
.init_arch = t2_init_arch,
|
|
.init_irq = sable_init_irq,
|
|
.init_rtc = common_init_rtc,
|
|
.init_pci = sable_lynx_init_pci,
|
|
.kill_arch = t2_kill_arch,
|
|
.pci_map_irq = sable_map_irq,
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
.sys = { .t2 = {
|
|
.gamma_bias = _GAMMA_BIAS
|
|
} }
|
|
};
|
|
ALIAS_MV(sable_gamma)
|
|
#endif /* GENERIC || (SABLE && GAMMA) */
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
|
|
#undef GAMMA_BIAS
|
|
#define GAMMA_BIAS _GAMMA_BIAS
|
|
struct alpha_machine_vector lynx_mv __initmv = {
|
|
.vector_name = "Lynx",
|
|
DO_EV4_MMU,
|
|
DO_DEFAULT_RTC,
|
|
DO_T2_IO,
|
|
.machine_check = t2_machine_check,
|
|
.max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
|
|
.min_io_address = EISA_DEFAULT_IO_BASE,
|
|
.min_mem_address = T2_DEFAULT_MEM_BASE,
|
|
|
|
.nr_irqs = 64,
|
|
.device_interrupt = sable_lynx_srm_device_interrupt,
|
|
|
|
.init_arch = t2_init_arch,
|
|
.init_irq = lynx_init_irq,
|
|
.init_rtc = common_init_rtc,
|
|
.init_pci = sable_lynx_init_pci,
|
|
.kill_arch = t2_kill_arch,
|
|
.pci_map_irq = lynx_map_irq,
|
|
.pci_swizzle = lynx_swizzle,
|
|
|
|
.sys = { .t2 = {
|
|
.gamma_bias = _GAMMA_BIAS
|
|
} }
|
|
};
|
|
ALIAS_MV(lynx)
|
|
#endif /* GENERIC || LYNX */
|