136 lines
3.9 KiB
Rust
136 lines
3.9 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2023 FUJITA Tomonori <fujita.tomonori@gmail.com>
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//! Rust Asix PHYs driver
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//!
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//! C version of this driver: [`drivers/net/phy/ax88796b.c`](./ax88796b.c)
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use kernel::{
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c_str,
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net::phy::{self, DeviceId, Driver},
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prelude::*,
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uapi,
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};
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kernel::module_phy_driver! {
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drivers: [PhyAX88772A, PhyAX88772C, PhyAX88796B],
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device_table: [
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DeviceId::new_with_driver::<PhyAX88772A>(),
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DeviceId::new_with_driver::<PhyAX88772C>(),
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DeviceId::new_with_driver::<PhyAX88796B>()
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],
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name: "rust_asix_phy",
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author: "FUJITA Tomonori <fujita.tomonori@gmail.com>",
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description: "Rust Asix PHYs driver",
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license: "GPL",
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}
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const MII_BMCR: u16 = uapi::MII_BMCR as u16;
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const BMCR_SPEED100: u16 = uapi::BMCR_SPEED100 as u16;
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const BMCR_FULLDPLX: u16 = uapi::BMCR_FULLDPLX as u16;
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// Performs a software PHY reset using the standard
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// BMCR_RESET bit and poll for the reset bit to be cleared.
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// Toggle BMCR_RESET bit off to accommodate broken AX8796B PHY implementation
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// such as used on the Individual Computers' X-Surf 100 Zorro card.
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fn asix_soft_reset(dev: &mut phy::Device) -> Result {
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dev.write(uapi::MII_BMCR as u16, 0)?;
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dev.genphy_soft_reset()
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}
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struct PhyAX88772A;
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#[vtable]
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impl Driver for PhyAX88772A {
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const FLAGS: u32 = phy::flags::IS_INTERNAL;
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const NAME: &'static CStr = c_str!("Asix Electronics AX88772A");
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const PHY_DEVICE_ID: DeviceId = DeviceId::new_with_exact_mask(0x003b1861);
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// AX88772A is not working properly with some old switches (NETGEAR EN 108TP):
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// after autoneg is done and the link status is reported as active, the MII_LPA
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// register is 0. This issue is not reproducible on AX88772C.
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fn read_status(dev: &mut phy::Device) -> Result<u16> {
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dev.genphy_update_link()?;
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if !dev.is_link_up() {
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return Ok(0);
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}
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// If MII_LPA is 0, phy_resolve_aneg_linkmode() will fail to resolve
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// linkmode so use MII_BMCR as default values.
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let ret = dev.read(MII_BMCR)?;
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if ret & BMCR_SPEED100 != 0 {
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dev.set_speed(uapi::SPEED_100);
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} else {
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dev.set_speed(uapi::SPEED_10);
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}
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let duplex = if ret & BMCR_FULLDPLX != 0 {
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phy::DuplexMode::Full
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} else {
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phy::DuplexMode::Half
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};
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dev.set_duplex(duplex);
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dev.genphy_read_lpa()?;
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if dev.is_autoneg_enabled() && dev.is_autoneg_completed() {
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dev.resolve_aneg_linkmode();
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}
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Ok(0)
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}
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fn suspend(dev: &mut phy::Device) -> Result {
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dev.genphy_suspend()
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}
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fn resume(dev: &mut phy::Device) -> Result {
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dev.genphy_resume()
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}
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fn soft_reset(dev: &mut phy::Device) -> Result {
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asix_soft_reset(dev)
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}
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fn link_change_notify(dev: &mut phy::Device) {
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// Reset PHY, otherwise MII_LPA will provide outdated information.
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// This issue is reproducible only with some link partner PHYs.
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if dev.state() == phy::DeviceState::NoLink {
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let _ = dev.init_hw();
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let _ = dev.start_aneg();
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}
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}
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}
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struct PhyAX88772C;
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#[vtable]
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impl Driver for PhyAX88772C {
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const FLAGS: u32 = phy::flags::IS_INTERNAL;
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const NAME: &'static CStr = c_str!("Asix Electronics AX88772C");
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const PHY_DEVICE_ID: DeviceId = DeviceId::new_with_exact_mask(0x003b1881);
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fn suspend(dev: &mut phy::Device) -> Result {
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dev.genphy_suspend()
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}
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fn resume(dev: &mut phy::Device) -> Result {
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dev.genphy_resume()
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}
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fn soft_reset(dev: &mut phy::Device) -> Result {
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asix_soft_reset(dev)
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}
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}
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struct PhyAX88796B;
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#[vtable]
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impl Driver for PhyAX88796B {
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const NAME: &'static CStr = c_str!("Asix Electronics AX88796B");
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const PHY_DEVICE_ID: DeviceId = DeviceId::new_with_model_mask(0x003b1841);
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fn soft_reset(dev: &mut phy::Device) -> Result {
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asix_soft_reset(dev)
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}
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}
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