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Normally, the clock source of audio module is either 26M or APLL1/APLL2, but APLL1/APLL2 are not the multiple of 26M. In the patch, APLL1 and APLL2 tuners are enabled to handle sample rate mismatch when the data path crosses two different clock domains. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Link: https://lore.kernel.org/r/20220221055716.18580-1-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition
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*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
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* Trevor Wu <trevor.wu@mediatek.com>
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*/
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#ifndef _MT8195_AFE_CLK_H_
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#define _MT8195_AFE_CLK_H_
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enum {
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/* xtal */
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MT8195_CLK_XTAL_26M,
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/* divider */
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MT8195_CLK_TOP_APLL1,
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MT8195_CLK_TOP_APLL2,
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MT8195_CLK_TOP_APLL12_DIV0,
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MT8195_CLK_TOP_APLL12_DIV1,
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MT8195_CLK_TOP_APLL12_DIV2,
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MT8195_CLK_TOP_APLL12_DIV3,
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MT8195_CLK_TOP_APLL12_DIV9,
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/* mux */
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MT8195_CLK_TOP_A1SYS_HP_SEL,
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MT8195_CLK_TOP_AUD_INTBUS_SEL,
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MT8195_CLK_TOP_AUDIO_H_SEL,
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MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
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MT8195_CLK_TOP_DPTX_M_SEL,
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MT8195_CLK_TOP_I2SO1_M_SEL,
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MT8195_CLK_TOP_I2SO2_M_SEL,
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MT8195_CLK_TOP_I2SI1_M_SEL,
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MT8195_CLK_TOP_I2SI2_M_SEL,
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/* clock gate */
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MT8195_CLK_INFRA_AO_AUDIO_26M_B,
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MT8195_CLK_SCP_ADSP_AUDIODSP,
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MT8195_CLK_AUD_AFE,
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MT8195_CLK_AUD_APLL1_TUNER,
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MT8195_CLK_AUD_APLL2_TUNER,
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MT8195_CLK_AUD_APLL,
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MT8195_CLK_AUD_APLL2,
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MT8195_CLK_AUD_DAC,
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MT8195_CLK_AUD_ADC,
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MT8195_CLK_AUD_DAC_HIRES,
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MT8195_CLK_AUD_A1SYS_HP,
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MT8195_CLK_AUD_ADC_HIRES,
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MT8195_CLK_AUD_ADDA6_ADC,
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MT8195_CLK_AUD_ADDA6_ADC_HIRES,
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MT8195_CLK_AUD_I2SIN,
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MT8195_CLK_AUD_TDM_IN,
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MT8195_CLK_AUD_I2S_OUT,
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MT8195_CLK_AUD_TDM_OUT,
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MT8195_CLK_AUD_HDMI_OUT,
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MT8195_CLK_AUD_ASRC11,
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MT8195_CLK_AUD_ASRC12,
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MT8195_CLK_AUD_A1SYS,
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MT8195_CLK_AUD_A2SYS,
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MT8195_CLK_AUD_PCMIF,
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MT8195_CLK_AUD_MEMIF_UL1,
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MT8195_CLK_AUD_MEMIF_UL2,
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MT8195_CLK_AUD_MEMIF_UL3,
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MT8195_CLK_AUD_MEMIF_UL4,
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MT8195_CLK_AUD_MEMIF_UL5,
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MT8195_CLK_AUD_MEMIF_UL6,
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MT8195_CLK_AUD_MEMIF_UL8,
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MT8195_CLK_AUD_MEMIF_UL9,
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MT8195_CLK_AUD_MEMIF_UL10,
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MT8195_CLK_AUD_MEMIF_DL2,
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MT8195_CLK_AUD_MEMIF_DL3,
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MT8195_CLK_AUD_MEMIF_DL6,
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MT8195_CLK_AUD_MEMIF_DL7,
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MT8195_CLK_AUD_MEMIF_DL8,
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MT8195_CLK_AUD_MEMIF_DL10,
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MT8195_CLK_AUD_MEMIF_DL11,
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MT8195_CLK_NUM,
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};
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enum {
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MT8195_MCK_SEL_26M,
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MT8195_MCK_SEL_APLL1,
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MT8195_MCK_SEL_APLL2,
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MT8195_MCK_SEL_APLL3,
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MT8195_MCK_SEL_APLL4,
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MT8195_MCK_SEL_APLL5,
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MT8195_MCK_SEL_HDMIRX_APLL,
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MT8195_MCK_SEL_NUM,
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};
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enum {
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MT8195_AUD_PLL1,
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MT8195_AUD_PLL2,
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MT8195_AUD_PLL3,
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MT8195_AUD_PLL4,
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MT8195_AUD_PLL5,
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MT8195_AUD_PLL_NUM,
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};
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struct mtk_base_afe;
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int mt8195_afe_get_mclk_source_clk_id(int sel);
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int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
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int mt8195_afe_get_default_mclk_source_by_rate(int rate);
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int mt8195_afe_init_clock(struct mtk_base_afe *afe);
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void mt8195_afe_deinit_clock(struct mtk_base_afe *afe);
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int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
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void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
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int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
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void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
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int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
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void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
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int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
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unsigned int rate);
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int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
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struct clk *parent);
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int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
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int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
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int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
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int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
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#endif
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