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d62ad762f6
This patch adds mt8195 audio cg control. Audio clock gates are registered to CCF for reference count and clock parent management. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Link: https://lore.kernel.org/r/20210819084144.18483-3-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
15 lines
386 B
C
15 lines
386 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock definition
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*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Trevor Wu <trevor.wu@mediatek.com>
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*/
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#ifndef _MT8195_AUDSYS_CLK_H_
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#define _MT8195_AUDSYS_CLK_H_
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int mt8195_audsys_clk_register(struct mtk_base_afe *afe);
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void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe);
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#endif
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