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These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM Conflicts: * In Kconfig.debug, various additions trivially conflict, the list should be kept in alphabetical order when resolving. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUdLnl2CrR//JCVInAQIrKhAAwvtsGNe6j9nDuLEitWtQAmhHYZQyUJ8k o9j/1j1CqhE8C0bLRud8D4m1GxfxbGeRm2d0HoNbxda3FmntUufqBDi6neMiQiLO VltC5rOYL8Mday0Asc3SBfjBj8SZC2bypicKy5zUfzsObCBt343g1WvYffMDNmwH FveOQK6q2BKmO67cazc9tk5xmxjVwP/LB8r5mQtiXmMguw0R+ZIDDIP6xaURFkxX SAElleD2wtvpVHP1d6AKHpXN99u3xV3uoJjKljECEXdBzW/ZX8m7FG2tKY5xy368 ta0Nhh2MSRnBhUYOH9uah4PQWYEsbZ+M/W+3J9tKRu6q9D/c/AAxILyXUY2tcHNC o1UwcUn1druirx3X1AW8HYAGNwW7BD3HANzIiUkQZG7ByfM4qCtUEo2SAFNIGBoR v1FMLhMPgMWotZnKrDQQd0anxkKIOFaSMRVgpQLW2jQt/B7sHLmEH2yDffkbSD76 PQDThnW/dfm9dgeK+X4fPrveIMKbjQlbFz0okN+LPsUf8e1045HBgCi2A0lTIGWM kVVgXHKKXi8G8HBa4VyDlORVHXk1bJEheF+zlDvdk4fHkcf+H/OfvFG2O9TdIdpb ITXRyyteaRM4YIZpnJbzeeZDZXT89c2ah7xq36iM+L1ScidyntPquViXeasSc8r6 pKu9ZDc0Mow= =cRu2 -----END PGP SIGNATURE----- Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late changes from Arnd Bergmann: "These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) ARM: ux500: bail out on alien cpus ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins serial: sh-sci: Initialise variables before access in sci_set_termios() ARM: stih41x: Add B2020 board support ARM: stih41x: Add B2000 board support ARM: sti: Add DEBUG_LL console support ARM: sti: Add STiH416 SOC support ARM: sti: Add STiH415 SOC support ARM: msm: Migrate to common clock framework ARM: msm: Make proc_comm clock control into a platform driver ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver ARM: msm: Remove clock-7x30.h include file ARM: msm: Remove custom clk_set_{max,min}_rate() API ARM: msm: Remove custom clk_set_flags() API msm: iommu: Use clk_set_rate() instead of clk_set_min_rate() msm: iommu: Convert to clk_prepare/unprepare msm_sdcc: Convert to clk_prepare/unprepare usb: otg: msm: Convert to clk_prepare/unprepare msm_serial: Use devm_clk_get() and properly return errors msm_serial: Convert to clk_prepare/unprepare ...
264 lines
8.5 KiB
C
264 lines
8.5 KiB
C
/*
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* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* http://www.linaro.org
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*
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __PINCTRL_SAMSUNG_H
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#define __PINCTRL_SAMSUNG_H
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/gpio.h>
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/* pinmux function number for pin as gpio output line */
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#define FUNC_OUTPUT 0x1
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/**
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* enum pincfg_type - possible pin configuration types supported.
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* @PINCFG_TYPE_FUNC: Function configuration.
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* @PINCFG_TYPE_DAT: Pin value configuration.
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* @PINCFG_TYPE_PUD: Pull up/down configuration.
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* @PINCFG_TYPE_DRV: Drive strength configuration.
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* @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
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* @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
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*/
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enum pincfg_type {
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PINCFG_TYPE_FUNC,
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PINCFG_TYPE_DAT,
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PINCFG_TYPE_PUD,
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PINCFG_TYPE_DRV,
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PINCFG_TYPE_CON_PDN,
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PINCFG_TYPE_PUD_PDN,
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PINCFG_TYPE_NUM
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};
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/*
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* pin configuration (pull up/down and drive strength) type and its value are
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* packed together into a 16-bits. The upper 8-bits represent the configuration
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* type and the lower 8-bits hold the value of the configuration type.
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*/
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#define PINCFG_TYPE_MASK 0xFF
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#define PINCFG_VALUE_SHIFT 8
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#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
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#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
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#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
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#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
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PINCFG_VALUE_SHIFT)
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/**
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* enum eint_type - possible external interrupt types.
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* @EINT_TYPE_NONE: bank does not support external interrupts
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* @EINT_TYPE_GPIO: bank supportes external gpio interrupts
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* @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
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* @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
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*
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* Samsung GPIO controller groups all the available pins into banks. The pins
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* in a pin bank can support external gpio interrupts or external wakeup
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* interrupts or no interrupts at all. From a software perspective, the only
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* difference between external gpio and external wakeup interrupts is that
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* the wakeup interrupts can additionally wakeup the system if it is in
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* suspended state.
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*/
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enum eint_type {
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EINT_TYPE_NONE,
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EINT_TYPE_GPIO,
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EINT_TYPE_WKUP,
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EINT_TYPE_WKUP_MUX,
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};
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/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
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#define PIN_NAME_LENGTH 10
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#define PIN_GROUP(n, p, f) \
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{ \
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.name = n, \
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.pins = p, \
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.num_pins = ARRAY_SIZE(p), \
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.func = f \
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}
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#define PMX_FUNC(n, g) \
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{ \
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.name = n, \
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.groups = g, \
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.num_groups = ARRAY_SIZE(g), \
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}
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struct samsung_pinctrl_drv_data;
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/**
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* struct samsung_pin_bank_type: pin bank type description
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* @fld_width: widths of configuration bitfields (0 if unavailable)
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* @reg_offset: offsets of configuration registers (don't care of width is 0)
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*/
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struct samsung_pin_bank_type {
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u8 fld_width[PINCFG_TYPE_NUM];
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u8 reg_offset[PINCFG_TYPE_NUM];
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};
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/**
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* struct samsung_pin_bank: represent a controller pin-bank.
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* @type: type of the bank (register offsets and bitfield widths)
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* @pctl_offset: starting offset of the pin-bank registers.
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* @pin_base: starting pin number of the bank.
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* @nr_pins: number of pins included in this bank.
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* @eint_func: function to set in CON register to configure pin as EINT.
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* @eint_type: type of the external interrupt supported by the bank.
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* @eint_mask: bit mask of pins which support EINT function.
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* @name: name to be prefixed for each pin in this pin bank.
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* @of_node: OF node of the bank.
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* @drvdata: link to controller driver data
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* @irq_domain: IRQ domain of the bank.
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* @gpio_chip: GPIO chip of the bank.
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* @grange: linux gpio pin range supported by this bank.
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* @slock: spinlock protecting bank registers
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* @pm_save: saved register values during suspend
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*/
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struct samsung_pin_bank {
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struct samsung_pin_bank_type *type;
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u32 pctl_offset;
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u32 pin_base;
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u8 nr_pins;
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u8 eint_func;
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enum eint_type eint_type;
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u32 eint_mask;
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u32 eint_offset;
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char *name;
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void *soc_priv;
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struct device_node *of_node;
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struct samsung_pinctrl_drv_data *drvdata;
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struct irq_domain *irq_domain;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range grange;
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spinlock_t slock;
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u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
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};
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/**
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* struct samsung_pin_ctrl: represent a pin controller.
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* @pin_banks: list of pin banks included in this controller.
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* @nr_banks: number of pin banks.
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* @base: starting system wide pin number.
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* @nr_pins: number of pins supported by the controller.
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* @geint_con: offset of the ext-gpio controller registers.
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* @geint_mask: offset of the ext-gpio interrupt mask registers.
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* @geint_pend: offset of the ext-gpio interrupt pending registers.
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* @weint_con: offset of the ext-wakeup controller registers.
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* @weint_mask: offset of the ext-wakeup interrupt mask registers.
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* @weint_pend: offset of the ext-wakeup interrupt pending registers.
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* @svc: offset of the interrupt service register.
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* @eint_gpio_init: platform specific callback to setup the external gpio
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* interrupts for the controller.
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* @eint_wkup_init: platform specific callback to setup the external wakeup
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* interrupts for the controller.
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* @label: for debug information.
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*/
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struct samsung_pin_ctrl {
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struct samsung_pin_bank *pin_banks;
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u32 nr_banks;
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u32 base;
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u32 nr_pins;
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u32 geint_con;
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u32 geint_mask;
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u32 geint_pend;
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u32 weint_con;
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u32 weint_mask;
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u32 weint_pend;
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u32 svc;
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int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
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int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
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void (*suspend)(struct samsung_pinctrl_drv_data *);
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void (*resume)(struct samsung_pinctrl_drv_data *);
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char *label;
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};
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/**
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* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
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* @node: global list node
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* @virt_base: register base address of the controller.
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* @dev: device instance representing the controller.
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* @irq: interrpt number used by the controller to notify gpio interrupts.
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* @ctrl: pin controller instance managed by the driver.
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* @pctl: pin controller descriptor registered with the pinctrl subsystem.
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* @pctl_dev: cookie representing pinctrl device instance.
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* @pin_groups: list of pin groups available to the driver.
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* @nr_groups: number of such pin groups.
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* @pmx_functions: list of pin functions available to the driver.
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* @nr_function: number of such pin functions.
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*/
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struct samsung_pinctrl_drv_data {
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struct list_head node;
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void __iomem *virt_base;
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struct device *dev;
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int irq;
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struct samsung_pin_ctrl *ctrl;
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struct pinctrl_desc pctl;
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struct pinctrl_dev *pctl_dev;
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const struct samsung_pin_group *pin_groups;
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unsigned int nr_groups;
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const struct samsung_pmx_func *pmx_functions;
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unsigned int nr_functions;
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};
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/**
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* struct samsung_pin_group: represent group of pins of a pinmux function.
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* @name: name of the pin group, used to lookup the group.
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* @pins: the pins included in this group.
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* @num_pins: number of pins included in this group.
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* @func: the function number to be programmed when selected.
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*/
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struct samsung_pin_group {
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const char *name;
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const unsigned int *pins;
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u8 num_pins;
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u8 func;
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};
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/**
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* struct samsung_pmx_func: represent a pin function.
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* @name: name of the pin function, used to lookup the function.
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* @groups: one or more names of pin groups that provide this function.
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* @num_groups: number of groups included in @groups.
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*/
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struct samsung_pmx_func {
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const char *name;
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const char **groups;
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u8 num_groups;
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};
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/* list of all exported SoC specific data */
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extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c2440_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c2450_pin_ctrl[];
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#endif /* __PINCTRL_SAMSUNG_H */
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