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2de451a329
An Armv8.8 FEAT_MOPS main or epilogue instruction will take an exception if executed on a CPU with a different MOPS implementation option (A or B) than the CPU where the preceding prologue instruction ran. In this case the OS exception handler is expected to reset the registers and restart execution from the prologue instruction. A KVM guest may use the instructions at EL1 at times when the guest is not able to handle the exception, expecting that the instructions will only run on one CPU (e.g. when running UEFI boot services in the guest). As KVM may reschedule the guest between different types of CPUs at any time (on an asymmetric system), it needs to also handle the resulting exception itself in case the guest is not able to. A similar situation will also occur in the future when live migrating a guest from one type of CPU to another. Add handling for the MOPS exception to KVM. The handling can be shared with the EL0 exception handler, as the logic and register layouts are the same. The exception can be handled right after exiting a guest, which avoids the cost of returning to the host exit handler. Similarly to the EL0 exception handler, in case the main or epilogue instruction is being single stepped, it makes sense to finish the step before executing the prologue instruction, so advance the single step state machine. Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230922112508.1774352-2-kristina.martsenko@arm.com Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
154 lines
4.3 KiB
C++
154 lines
4.3 KiB
C++
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/traps.h
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*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_TRAP_H
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#define __ASM_TRAP_H
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#include <linux/list.h>
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#include <asm/esr.h>
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#include <asm/ptrace.h>
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#include <asm/sections.h>
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#ifdef CONFIG_ARMV8_DEPRECATED
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bool try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn);
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#else
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static inline bool
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try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn)
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{
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return false;
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}
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#endif /* CONFIG_ARMV8_DEPRECATED */
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void force_signal_inject(int signal, int code, unsigned long address, unsigned long err);
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void arm64_notify_segfault(unsigned long addr);
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void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str);
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void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str);
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void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str);
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int early_brk64(unsigned long addr, unsigned long esr, struct pt_regs *regs);
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/*
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* Move regs->pc to next instruction and do necessary setup before it
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* is executed.
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*/
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void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
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static inline int __in_irqentry_text(unsigned long ptr)
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{
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return ptr >= (unsigned long)&__irqentry_text_start &&
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ptr < (unsigned long)&__irqentry_text_end;
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}
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static inline int in_entry_text(unsigned long ptr)
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{
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return ptr >= (unsigned long)&__entry_text_start &&
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ptr < (unsigned long)&__entry_text_end;
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}
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/*
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* CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
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* to indicate whether this ESR has a RAS encoding. CPUs without this feature
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* have a ISS-Valid bit in the same position.
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* If this bit is set, we know its not a RAS SError.
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* If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
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* errors share the same encoding as an all-zeros encoding from a CPU that
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* doesn't support RAS.
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*/
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static inline bool arm64_is_ras_serror(unsigned long esr)
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{
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WARN_ON(preemptible());
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if (esr & ESR_ELx_IDS)
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return false;
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if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
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return true;
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else
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return false;
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}
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/*
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* Return the AET bits from a RAS SError's ESR.
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*
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* It is implementation defined whether Uncategorized errors are containable.
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* We treat them as Uncontainable.
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* Non-RAS SError's are reported as Uncontained/Uncategorized.
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*/
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static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr)
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{
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unsigned long aet = esr & ESR_ELx_AET;
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if (!arm64_is_ras_serror(esr)) {
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/* Not a RAS error, we can't interpret the ESR. */
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return ESR_ELx_AET_UC;
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}
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/*
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* AET is RES0 if 'the value returned in the DFSC field is not
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* [ESR_ELx_FSC_SERROR]'
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*/
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if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
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/* No severity information : Uncategorized */
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return ESR_ELx_AET_UC;
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}
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return aet;
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}
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bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr);
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void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr);
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static inline void arm64_mops_reset_regs(struct user_pt_regs *regs, unsigned long esr)
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{
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bool wrong_option = esr & ESR_ELx_MOPS_ISS_WRONG_OPTION;
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bool option_a = esr & ESR_ELx_MOPS_ISS_OPTION_A;
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int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr);
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int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr);
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int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr);
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unsigned long dst, src, size;
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dst = regs->regs[dstreg];
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src = regs->regs[srcreg];
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size = regs->regs[sizereg];
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/*
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* Put the registers back in the original format suitable for a
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* prologue instruction, using the generic return routine from the
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* Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH.
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*/
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if (esr & ESR_ELx_MOPS_ISS_MEM_INST) {
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/* SET* instruction */
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if (option_a ^ wrong_option) {
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/* Format is from Option A; forward set */
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regs->regs[dstreg] = dst + size;
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regs->regs[sizereg] = -size;
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}
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} else {
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/* CPY* instruction */
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if (!(option_a ^ wrong_option)) {
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/* Format is from Option B */
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if (regs->pstate & PSR_N_BIT) {
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/* Backward copy */
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regs->regs[dstreg] = dst - size;
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regs->regs[srcreg] = src - size;
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}
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} else {
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/* Format is from Option A */
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if (size & BIT(63)) {
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/* Forward copy */
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regs->regs[dstreg] = dst + size;
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regs->regs[srcreg] = src + size;
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regs->regs[sizereg] = -size;
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}
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}
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}
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if (esr & ESR_ELx_MOPS_ISS_FROM_EPILOGUE)
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regs->pc -= 8;
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else
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regs->pc -= 4;
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}
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#endif
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