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5c5416f5d4
It was a waste to clone skb directly in dsa_skb_tx_timestamp(). For one-step timestamping, a clone was not needed. For any failure of port_txtstamp (this may usually happen), the skb clone had to be freed. So this patch moves skb cloning for tx timestamp out of dsa core, and let drivers clone skb in port_txtstamp if they really need. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Kurt Kanzenbach <kurt@linutronix.de> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
176 lines
5.4 KiB
C
176 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Marvell 88E6xxx Switch hardware timestamping support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2017 National Instruments
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* Erik Hons <erik.hons@ni.com>
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* Brandon Streiff <brandon.streiff@ni.com>
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* Dane Wagner <dane.wagner@ni.com>
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*/
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#ifndef _MV88E6XXX_HWTSTAMP_H
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#define _MV88E6XXX_HWTSTAMP_H
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#include "chip.h"
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/* Global 6352 PTP registers */
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/* Offset 0x00: PTP EtherType */
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#define MV88E6XXX_PTP_ETHERTYPE 0x00
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/* Offset 0x01: Message Type Timestamp Enables */
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#define MV88E6XXX_PTP_MSGTYPE 0x01
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#define MV88E6XXX_PTP_MSGTYPE_SYNC 0x0001
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#define MV88E6XXX_PTP_MSGTYPE_DELAY_REQ 0x0002
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#define MV88E6XXX_PTP_MSGTYPE_PDLAY_REQ 0x0004
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#define MV88E6XXX_PTP_MSGTYPE_PDLAY_RES 0x0008
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#define MV88E6XXX_PTP_MSGTYPE_ALL_EVENT 0x000f
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/* Offset 0x02: Timestamp Arrival Capture Pointers */
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#define MV88E6XXX_PTP_TS_ARRIVAL_PTR 0x02
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/* Offset 0x05: PTP Global Configuration */
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#define MV88E6165_PTP_CFG 0x05
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#define MV88E6165_PTP_CFG_TSPEC_MASK 0xf000
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#define MV88E6165_PTP_CFG_DISABLE_TS_OVERWRITE BIT(1)
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#define MV88E6165_PTP_CFG_DISABLE_PTP BIT(0)
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/* Offset 0x07: PTP Global Configuration */
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#define MV88E6341_PTP_CFG 0x07
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#define MV88E6341_PTP_CFG_UPDATE 0x8000
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#define MV88E6341_PTP_CFG_IDX_MASK 0x7f00
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#define MV88E6341_PTP_CFG_DATA_MASK 0x00ff
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#define MV88E6341_PTP_CFG_MODE_IDX 0x0
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#define MV88E6341_PTP_CFG_MODE_TS_AT_PHY 0x00
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#define MV88E6341_PTP_CFG_MODE_TS_AT_MAC 0x80
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/* Offset 0x08: PTP Interrupt Status */
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#define MV88E6XXX_PTP_IRQ_STATUS 0x08
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/* Per-Port 6352 PTP Registers */
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/* Offset 0x00: PTP Configuration 0 */
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#define MV88E6XXX_PORT_PTP_CFG0 0x00
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#define MV88E6XXX_PORT_PTP_CFG0_TSPEC_SHIFT 12
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#define MV88E6XXX_PORT_PTP_CFG0_TSPEC_MASK 0xf000
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#define MV88E6XXX_PORT_PTP_CFG0_TSPEC_1588 0x0000
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#define MV88E6XXX_PORT_PTP_CFG0_TSPEC_8021AS 0x1000
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#define MV88E6XXX_PORT_PTP_CFG0_DISABLE_TSPEC_MATCH 0x0800
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#define MV88E6XXX_PORT_PTP_CFG0_DISABLE_OVERWRITE 0x0002
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#define MV88E6XXX_PORT_PTP_CFG0_DISABLE_PTP 0x0001
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/* Offset 0x01: PTP Configuration 1 */
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#define MV88E6XXX_PORT_PTP_CFG1 0x01
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/* Offset 0x02: PTP Configuration 2 */
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#define MV88E6XXX_PORT_PTP_CFG2 0x02
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#define MV88E6XXX_PORT_PTP_CFG2_EMBED_ARRIVAL 0x1000
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#define MV88E6XXX_PORT_PTP_CFG2_DEP_IRQ_EN 0x0002
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#define MV88E6XXX_PORT_PTP_CFG2_ARR_IRQ_EN 0x0001
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/* Offset 0x03: PTP LED Configuration */
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#define MV88E6XXX_PORT_PTP_LED_CFG 0x03
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/* Offset 0x08: PTP Arrival 0 Status */
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#define MV88E6XXX_PORT_PTP_ARR0_STS 0x08
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/* Offset 0x09/0x0A: PTP Arrival 0 Time */
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#define MV88E6XXX_PORT_PTP_ARR0_TIME_LO 0x09
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#define MV88E6XXX_PORT_PTP_ARR0_TIME_HI 0x0a
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/* Offset 0x0B: PTP Arrival 0 Sequence ID */
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#define MV88E6XXX_PORT_PTP_ARR0_SEQID 0x0b
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/* Offset 0x0C: PTP Arrival 1 Status */
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#define MV88E6XXX_PORT_PTP_ARR1_STS 0x0c
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/* Offset 0x0D/0x0E: PTP Arrival 1 Time */
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#define MV88E6XXX_PORT_PTP_ARR1_TIME_LO 0x0d
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#define MV88E6XXX_PORT_PTP_ARR1_TIME_HI 0x0e
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/* Offset 0x0F: PTP Arrival 1 Sequence ID */
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#define MV88E6XXX_PORT_PTP_ARR1_SEQID 0x0f
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/* Offset 0x10: PTP Departure Status */
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#define MV88E6XXX_PORT_PTP_DEP_STS 0x10
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/* Offset 0x11/0x12: PTP Deperture Time */
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#define MV88E6XXX_PORT_PTP_DEP_TIME_LO 0x11
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#define MV88E6XXX_PORT_PTP_DEP_TIME_HI 0x12
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/* Offset 0x13: PTP Departure Sequence ID */
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#define MV88E6XXX_PORT_PTP_DEP_SEQID 0x13
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/* Status fields for arrival and depature timestamp status registers */
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#define MV88E6XXX_PTP_TS_STATUS_MASK 0x0006
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#define MV88E6XXX_PTP_TS_STATUS_NORMAL 0x0000
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#define MV88E6XXX_PTP_TS_STATUS_OVERWITTEN 0x0002
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#define MV88E6XXX_PTP_TS_STATUS_DISCARDED 0x0004
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#define MV88E6XXX_PTP_TS_VALID 0x0001
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#ifdef CONFIG_NET_DSA_MV88E6XXX_PTP
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int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, int port,
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struct ifreq *ifr);
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int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, int port,
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struct ifreq *ifr);
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bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port,
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struct sk_buff *clone, unsigned int type);
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void mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port,
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struct sk_buff *skb);
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int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port,
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struct ethtool_ts_info *info);
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int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip);
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void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip);
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int mv88e6352_hwtstamp_port_enable(struct mv88e6xxx_chip *chip, int port);
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int mv88e6352_hwtstamp_port_disable(struct mv88e6xxx_chip *chip, int port);
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int mv88e6165_global_enable(struct mv88e6xxx_chip *chip);
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int mv88e6165_global_disable(struct mv88e6xxx_chip *chip);
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#else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */
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static inline int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds,
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int port, struct ifreq *ifr)
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{
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return -EOPNOTSUPP;
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}
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static inline int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds,
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int port, struct ifreq *ifr)
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{
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return -EOPNOTSUPP;
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}
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static inline bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port,
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struct sk_buff *clone,
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unsigned int type)
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{
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return false;
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}
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static inline void mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port,
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struct sk_buff *skb)
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{
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}
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static inline int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port,
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struct ethtool_ts_info *info)
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{
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return -EOPNOTSUPP;
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}
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static inline int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip)
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{
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return 0;
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}
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static inline void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip)
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{
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}
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#endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */
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#endif /* _MV88E6XXX_HWTSTAMP_H */
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