Michael Kelley 4732ac1c23 PCI: hv: Fix ring buffer size calculation ... [ Upstream commit b5ff74c1ef ] For a physical PCI device that is passed through to a Hyper-V guest VM, current code specifies the VMBus ring buffer size as 4 pages. But this is an inappropriate dependency, since the amount of ring buffer space needed is unrelated to PAGE_SIZE. For example, on x86 the ring buffer size ends up as 16 Kbytes, while on ARM64 with 64 Kbyte pages, the ring size bloats to 256 Kbytes. The ring buffer for PCI pass-thru devices is used for only a few messages during device setup and removal, so any space above a few Kbytes is wasted. Fix this by declaring the ring buffer size to be a fixed 16 Kbytes. Furthermore, use the VMBUS_RING_SIZE() macro so that the ring buffer header is properly accounted for, and so the size is rounded up to a page boundary, using the page size for which the kernel is built. While w/64 Kbyte pages this results in a 64 Kbyte ring buffer header plus a 64 Kbyte ring buffer, that's the smallest possible with that page size. It's still 128 Kbytes better than the current code. Link: https://lore.kernel.org/linux-pci/20240216202240.251818-1-mhklinux@outlook.com Signed-off-by: Michael Kelley <mhklinux@outlook.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Ilpo Jarvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Long Li <longli@microsoft.com> Cc: <stable@vger.kernel.org> # 5.15.x Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-04-03 15:19:34 +02:00
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cadence	PCI: cadence: Fix Gen2 Link Retraining process	2023-07-19 16:21:34 +02:00
dwc	PCI: dwc: endpoint: Fix advertised resizable BAR size	2024-04-03 15:19:34 +02:00
mobiveil
Kconfig
Makefile
pci-aardvark.c
pci-ftpci100.c	PCI: ftpci100: Release the clock resources	2023-07-19 16:21:35 +02:00
pci-host-common.c
pci-host-generic.c
pci-hyperv-intf.c
pci-hyperv.c	PCI: hv: Fix ring buffer size calculation	2024-04-03 15:19:34 +02:00
pci-ixp4xx.c
pci-loongson.c	PCI: loongson: Limit MRRS to 256	2023-12-20 17:00:20 +01:00
pci-mvebu.c	PCI: mvebu: Use FIELD_PREP() with Link Width	2023-11-28 17:06:59 +00:00
pci-rcar-gen2.c
pci-tegra.c
pci-thunder-ecam.c
pci-thunder-pem.c
pci-v3-semi.c
pci-versatile.c
pci-xgene-msi.c
pci-xgene.c
pcie-altera-msi.c
pcie-altera.c
pcie-apple.c	PCI: apple: Initialize pcie->nvecs before use	2023-09-13 09:42:45 +02:00
pcie-brcmstb.c
pcie-hisi-error.c
pcie-iproc-bcma.c
pcie-iproc-msi.c
pcie-iproc-platform.c
pcie-iproc.c
pcie-iproc.h
pcie-mediatek-gen3.c	PCI: mediatek-gen3: Fix translation window size calculation	2024-01-25 15:27:48 -08:00
pcie-mediatek.c	PCI: mediatek: Clear interrupt status before dispatching handler	2024-01-25 15:27:44 -08:00
pcie-microchip-host.c	PCI: microchip: Correct the DED and SEC interrupt bit offsets	2023-09-13 09:42:46 +02:00
pcie-mt7621.c
pcie-rcar-ep.c
pcie-rcar-host.c
pcie-rcar.c
pcie-rcar.h
pcie-rockchip-ep.c	PCI: rockchip: Don't advertise MSI-X in PCIe capabilities	2023-08-03 10:23:51 +02:00
pcie-rockchip-host.c
pcie-rockchip.c	PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked	2023-07-23 13:49:36 +02:00
pcie-rockchip.h	PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI address	2023-09-13 09:43:00 +02:00
pcie-xilinx-cpm.c
pcie-xilinx-nwl.c
pcie-xilinx.c
vmd.c	PCI: vmd: Correct PCI Header Type Register's multi-function check	2023-11-20 11:52:05 +01:00