Chao Xie cdce35460f clk: mmp: add mmp private gate clock ... Some SOCes have this kind of the gate clock 1. There are some bits to control the gate not only one bit. 2. It is not always that "1" is to enable while "0" is to disable when write register. So we have to define the "mask", "enable_val", "disable_val" for this kind of gate clock. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>		2014-11-12 16:34:00 -08:00
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clk-apbc.c
clk-apmu.c
clk-frac.c	clk: mmp: move definiton of mmp_clk_frac to clk.h	2014-11-12 16:33:48 -08:00
clk-gate.c	clk: mmp: add mmp private gate clock	2014-11-12 16:34:00 -08:00
clk-mix.c	clk: mmp: add clock type mix	2014-11-12 16:33:52 -08:00
clk-mmp2.c	clk: mmp: add spin lock for clk-frac	2014-11-12 16:33:37 -08:00
clk-pxa168.c	clk: mmp: add spin lock for clk-frac	2014-11-12 16:33:37 -08:00
clk-pxa910.c	clk: mmp: add spin lock for clk-frac	2014-11-12 16:33:37 -08:00
clk.h	clk: mmp: add mmp private gate clock	2014-11-12 16:34:00 -08:00
Makefile	clk: mmp: add mmp private gate clock	2014-11-12 16:34:00 -08:00