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cdd5df644a
Use more straight-forward definitions for multi-bit field of PANEL_PLL_CTRL register and use open-coded implementation for register manipulations. Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
383 lines
9.4 KiB
C
383 lines
9.4 KiB
C
#include <linux/sizes.h>
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#include "ddk750_help.h"
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#include "ddk750_reg.h"
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#include "ddk750_chip.h"
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#include "ddk750_power.h"
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logical_chip_type_t getChipType(void)
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{
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unsigned short physicalID;
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char physicalRev;
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logical_chip_type_t chip;
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physicalID = devId750; /* either 0x718 or 0x750 */
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physicalRev = revId750;
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if (physicalID == 0x718)
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chip = SM718;
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else if (physicalID == 0x750) {
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chip = SM750;
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/* SM750 and SM750LE are different in their revision ID only. */
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if (physicalRev == SM750LE_REVISION_ID)
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chip = SM750LE;
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} else
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chip = SM_UNKNOWN;
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return chip;
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}
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static unsigned int get_mxclk_freq(void)
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{
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unsigned int pll_reg;
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unsigned int M, N, OD, POD;
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if (getChipType() == SM750LE)
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return MHz(130);
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pll_reg = PEEK32(MXCLK_PLL_CTRL);
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M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
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N = (pll_reg & PLL_CTRL_N_MASK) >> PLL_CTRL_M_SHIFT;
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OD = (pll_reg & PLL_CTRL_OD_MASK) >> PLL_CTRL_OD_SHIFT;
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POD = (pll_reg & PLL_CTRL_POD_MASK) >> PLL_CTRL_POD_SHIFT;
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return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD);
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}
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/*
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* This function set up the main chip clock.
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*
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* Input: Frequency to be set.
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*/
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static void setChipClock(unsigned int frequency)
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{
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pll_value_t pll;
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unsigned int ulActualMxClk;
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/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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return;
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if (frequency) {
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/*
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* Set up PLL, a structure to hold the value to be set in clocks.
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*/
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pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
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pll.clockType = MXCLK_PLL;
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/*
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* Call calcPllValue() to fill up the other fields for PLL structure.
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* Sometime, the chip cannot set up the exact clock required by User.
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* Return value from calcPllValue() gives the actual possible clock.
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*/
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ulActualMxClk = calcPllValue(frequency, &pll);
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/* Master Clock Control: MXCLK_PLL */
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POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll));
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}
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}
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static void setMemoryClock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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return;
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if (frequency) {
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/* Set the frequency to the maximum frequency that the DDR Memory can take
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which is 336MHz. */
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if (frequency > MHz(336))
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frequency = MHz(336);
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/* Calculate the divisor */
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divisor = roundedDiv(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
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switch (divisor) {
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default:
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case 1:
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reg |= CURRENT_GATE_M2XCLK_DIV_1;
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break;
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case 2:
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reg |= CURRENT_GATE_M2XCLK_DIV_2;
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break;
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case 3:
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reg |= CURRENT_GATE_M2XCLK_DIV_3;
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break;
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case 4:
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reg |= CURRENT_GATE_M2XCLK_DIV_4;
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break;
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}
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setCurrentGate(reg);
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}
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}
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/*
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* This function set up the master clock (MCLK).
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*
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* Input: Frequency to be set.
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*
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* NOTE:
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* The maximum frequency the engine can run is 168MHz.
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*/
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static void setMasterClock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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return;
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if (frequency) {
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/* Set the frequency to the maximum frequency that the SM750 engine can
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run, which is about 190 MHz. */
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if (frequency > MHz(190))
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frequency = MHz(190);
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/* Calculate the divisor */
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divisor = roundedDiv(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK;
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switch (divisor) {
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default:
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case 3:
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reg |= CURRENT_GATE_MCLK_DIV_3;
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break;
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case 4:
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reg |= CURRENT_GATE_MCLK_DIV_4;
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break;
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case 6:
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reg |= CURRENT_GATE_MCLK_DIV_6;
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break;
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case 8:
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reg |= CURRENT_GATE_MCLK_DIV_8;
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break;
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}
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setCurrentGate(reg);
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}
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}
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unsigned int ddk750_getVMSize(void)
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{
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unsigned int reg;
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unsigned int data;
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/* sm750le only use 64 mb memory*/
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if (getChipType() == SM750LE)
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return SZ_64M;
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/* for 750,always use power mode0*/
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reg = PEEK32(MODE0_GATE);
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reg |= MODE0_GATE_GPIO;
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POKE32(MODE0_GATE, reg);
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/* get frame buffer size from GPIO */
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reg = PEEK32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK;
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switch (reg) {
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case MISC_CTRL_LOCALMEM_SIZE_8M:
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data = SZ_8M; break; /* 8 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_16M:
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data = SZ_16M; break; /* 16 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_32M:
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data = SZ_32M; break; /* 32 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_64M:
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data = SZ_64M; break; /* 64 Mega byte */
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default:
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data = 0;
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break;
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}
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return data;
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}
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int ddk750_initHw(initchip_param_t *pInitParam)
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{
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unsigned int reg;
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if (pInitParam->powerMode != 0)
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pInitParam->powerMode = 0;
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setPowerMode(pInitParam->powerMode);
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/* Enable display power gate & LOCALMEM power gate*/
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reg = PEEK32(CURRENT_GATE);
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reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
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setCurrentGate(reg);
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if (getChipType() != SM750LE) {
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/* set panel pll and graphic mode via mmio_88 */
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reg = PEEK32(VGA_CONFIGURATION);
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reg = FIELD_SET(reg, VGA_CONFIGURATION, PLL, PANEL);
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reg = FIELD_SET(reg, VGA_CONFIGURATION, MODE, GRAPHIC);
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POKE32(VGA_CONFIGURATION, reg);
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} else {
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#if defined(__i386__) || defined(__x86_64__)
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/* set graphic mode via IO method */
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outb_p(0x88, 0x3d4);
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outb_p(0x06, 0x3d5);
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#endif
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}
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/* Set the Main Chip Clock */
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setChipClock(MHz((unsigned int)pInitParam->chipClock));
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/* Set up memory clock. */
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setMemoryClock(MHz(pInitParam->memClock));
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/* Set up master clock */
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setMasterClock(MHz(pInitParam->masterClock));
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/* Reset the memory controller. If the memory controller is not reset in SM750,
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the system might hang when sw accesses the memory.
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The memory should be resetted after changing the MXCLK.
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*/
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if (pInitParam->resetMemory == 1) {
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reg = PEEK32(MISC_CTRL);
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reg &= ~MISC_CTRL_LOCALMEM_RESET;
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POKE32(MISC_CTRL, reg);
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reg |= MISC_CTRL_LOCALMEM_RESET;
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POKE32(MISC_CTRL, reg);
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}
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if (pInitParam->setAllEngOff == 1) {
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enable2DEngine(0);
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/* Disable Overlay, if a former application left it on */
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reg = PEEK32(VIDEO_DISPLAY_CTRL);
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reg = FIELD_SET(reg, VIDEO_DISPLAY_CTRL, PLANE, DISABLE);
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POKE32(VIDEO_DISPLAY_CTRL, reg);
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/* Disable video alpha, if a former application left it on */
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reg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL);
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reg = FIELD_SET(reg, VIDEO_ALPHA_DISPLAY_CTRL, PLANE, DISABLE);
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POKE32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
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/* Disable alpha plane, if a former application left it on */
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reg = PEEK32(ALPHA_DISPLAY_CTRL);
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reg = FIELD_SET(reg, ALPHA_DISPLAY_CTRL, PLANE, DISABLE);
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POKE32(ALPHA_DISPLAY_CTRL, reg);
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/* Disable DMA Channel, if a former application left it on */
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reg = PEEK32(DMA_ABORT_INTERRUPT);
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reg = FIELD_SET(reg, DMA_ABORT_INTERRUPT, ABORT_1, ABORT);
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POKE32(DMA_ABORT_INTERRUPT, reg);
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/* Disable DMA Power, if a former application left it on */
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enableDMA(0);
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}
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/* We can add more initialization as needed. */
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return 0;
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}
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/*
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monk liu @ 4/6/2011:
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re-write the calculatePLL function of ddk750.
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the original version function does not use some mathematics tricks and shortcut
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when it doing the calculation of the best N,M,D combination
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I think this version gives a little upgrade in speed
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750 pll clock formular:
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Request Clock = (Input Clock * M )/(N * X)
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Input Clock = 14318181 hz
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X = 2 power D
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D ={0,1,2,3,4,5,6}
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M = {1,...,255}
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N = {2,...,15}
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*/
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unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll)
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{
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/* as sm750 register definition, N located in 2,15 and M located in 1,255 */
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int N, M, X, d;
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int mini_diff;
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unsigned int RN, quo, rem, fl_quo;
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unsigned int input, request;
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unsigned int tmpClock, ret;
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const int max_OD = 3;
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int max_d;
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if (getChipType() == SM750LE) {
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/* SM750LE don't have prgrammable PLL and M/N values to work on.
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Just return the requested clock. */
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return request_orig;
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}
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ret = 0;
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mini_diff = ~0;
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request = request_orig / 1000;
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input = pll->inputFreq / 1000;
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/* for MXCLK register , no POD provided, so need be treated differently */
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if (pll->clockType == MXCLK_PLL)
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max_d = 3;
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for (N = 15; N > 1; N--) {
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/* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */
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RN = N * request;
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quo = RN / input;
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rem = RN % input;/* rem always small than 14318181 */
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fl_quo = (rem * 10000 / input);
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for (d = max_d; d >= 0; d--) {
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X = (1 << d);
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M = quo * X;
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M += fl_quo * X / 10000;
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/* round step */
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M += (fl_quo * X % 10000) > 5000 ? 1 : 0;
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if (M < 256 && M > 0) {
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unsigned int diff;
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tmpClock = pll->inputFreq * M / N / X;
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diff = absDiff(tmpClock, request_orig);
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if (diff < mini_diff) {
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pll->M = M;
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pll->N = N;
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pll->POD = 0;
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if (d > max_OD)
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pll->POD = d - max_OD;
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pll->OD = d - pll->POD;
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mini_diff = diff;
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ret = tmpClock;
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}
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}
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}
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}
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return ret;
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}
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unsigned int formatPllReg(pll_value_t *pPLL)
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{
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#ifndef VALIDATION_CHIP
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unsigned int POD = pPLL->POD;
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#endif
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unsigned int OD = pPLL->OD;
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unsigned int M = pPLL->M;
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unsigned int N = pPLL->N;
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unsigned int reg = 0;
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/*
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* Note that all PLL's have the same format. Here, we just use
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* Panel PLL parameter to work out the bit fields in the
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* register. On returning a 32 bit number, the value can be
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* applied to any PLL in the calling function.
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*/
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reg = PLL_CTRL_POWER |
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#ifndef VALIDATION_CHIP
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((POD << PLL_CTRL_POD_SHIFT) & PLL_CTRL_POD_MASK) |
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#endif
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((OD << PLL_CTRL_OD_SHIFT) & PLL_CTRL_OD_MASK) |
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((N << PLL_CTRL_N_SHIFT) & PLL_CTRL_N_MASK) |
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((M << PLL_CTRL_M_SHIFT) & PLL_CTRL_M_MASK);
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return reg;
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}
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