mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-15 23:25:07 +00:00
3e1aa7cb59
By the nature of the TEST operation, it is often possible to test
a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
This results in shorter instructions, because the TEST instruction
has no sign-entending byte-immediate forms unlike other ALU ops.
Note that this change does not create any LCP (Length-Changing Prefix)
stalls, which happen when adding a 0x66 prefix, which happens when
16-bit immediates are used, which changes such TEST instructions:
[test_opcode] [modrm] [imm32]
to:
[0x66] [test_opcode] [modrm] [imm16]
where [imm16] has a *different length* now: 2 bytes instead of 4.
This confuses the decoder and slows down execution.
REX prefixes were carefully designed to almost never hit this case:
adding REX prefix does not change instruction length except MOVABS
and MOV [addr],RAX instruction.
This patch does not add instructions which would use a 0x66 prefix,
code changes in assembly are:
-48 f7 07 01 00 00 00 testq $0x1,(%rdi)
+f6 07 01 testb $0x1,(%rdi)
-48 f7 c1 01 00 00 00 test $0x1,%rcx
+f6 c1 01 test $0x1,%cl
-48 f7 c1 02 00 00 00 test $0x2,%rcx
+f6 c1 02 test $0x2,%cl
-41 f7 c2 01 00 00 00 test $0x1,%r10d
+41 f6 c2 01 test $0x1,%r10b
-48 f7 c1 04 00 00 00 test $0x4,%rcx
+f6 c1 04 test $0x4,%cl
-48 f7 c1 08 00 00 00 test $0x8,%rcx
+f6 c1 08 test $0x8,%cl
Linus further notes:
"There are no stalls from using 8-bit instruction forms.
Now, changing from 64-bit or 32-bit 'test' instructions to 8-bit ones
*could* cause problems if it ends up having forwarding issues, so that
instead of just forwarding the result, you end up having to wait for
it to be stable in the L1 cache (or possibly the register file). The
forwarding from the store buffer is simplest and most reliable if the
read is done at the exact same address and the exact same size as the
write that gets forwarded.
But that's true only if:
(a) the write was very recent and is still in the write queue. I'm
not sure that's the case here anyway.
(b) on at least most Intel microarchitectures, you have to test a
different byte than the lowest one (so forwarding a 64-bit write
to a 8-bit read ends up working fine, as long as the 8-bit read
is of the low 8 bits of the written data).
A very similar issue *might* show up for registers too, not just
memory writes, if you use 'testb' with a high-byte register (where
instead of forwarding the value from the original producer it needs to
go through the register file and then shifted). But it's mainly a
problem for store buffers.
But afaik, the way Denys changed the test instructions, neither of the
above issues should be true.
The real problem for store buffer forwarding tends to be "write 8
bits, read 32 bits". That can be really surprisingly expensive,
because the read ends up having to wait until the write has hit the
cacheline, and we might talk tens of cycles of latency here. But
"write 32 bits, read the low 8 bits" *should* be fast on pretty much
all x86 chips, afaik."
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1425675332-31576-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
502 lines
10 KiB
ArmAsm
502 lines
10 KiB
ArmAsm
/*
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* INET An implementation of the TCP/IP protocol suite for the LINUX
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* operating system. INET is implemented using the BSD Socket
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* interface as the means of communication with the user level.
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*
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* IP/TCP/UDP checksumming routines
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*
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* Authors: Jorge Cwik, <jorge@laser.satlink.net>
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* Arnt Gulbrandsen, <agulbra@nvg.unit.no>
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* Tom May, <ftom@netcom.com>
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* Pentium Pro/II routines:
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* Alexander Kjeldaas <astor@guardian.no>
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* Finn Arne Gangstad <finnag@guardian.no>
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* Lots of code moved from tcp.c and ip.c; see those files
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* for more names.
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*
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* Changes: Ingo Molnar, converted csum_partial_copy() to 2.1 exception
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* handling.
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* Andi Kleen, add zeroing on error
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* converted to pure assembler
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/linkage.h>
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#include <asm/dwarf2.h>
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#include <asm/errno.h>
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#include <asm/asm.h>
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/*
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* computes a partial checksum, e.g. for TCP/UDP fragments
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*/
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/*
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unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum)
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*/
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.text
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#ifndef CONFIG_X86_USE_PPRO_CHECKSUM
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/*
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* Experiments with Ethernet and SLIP connections show that buff
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* is aligned on either a 2-byte or 4-byte boundary. We get at
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* least a twofold speedup on 486 and Pentium if it is 4-byte aligned.
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* Fortunately, it is easy to convert 2-byte alignment to 4-byte
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* alignment for the unrolled loop.
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*/
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ENTRY(csum_partial)
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CFI_STARTPROC
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pushl_cfi_reg esi
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pushl_cfi_reg ebx
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movl 20(%esp),%eax # Function arg: unsigned int sum
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movl 16(%esp),%ecx # Function arg: int len
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movl 12(%esp),%esi # Function arg: unsigned char *buff
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testl $3, %esi # Check alignment.
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jz 2f # Jump if alignment is ok.
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testl $1, %esi # Check alignment.
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jz 10f # Jump if alignment is boundary of 2 bytes.
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# buf is odd
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dec %ecx
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jl 8f
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movzbl (%esi), %ebx
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adcl %ebx, %eax
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roll $8, %eax
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inc %esi
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testl $2, %esi
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jz 2f
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10:
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subl $2, %ecx # Alignment uses up two bytes.
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jae 1f # Jump if we had at least two bytes.
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addl $2, %ecx # ecx was < 2. Deal with it.
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jmp 4f
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1: movw (%esi), %bx
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addl $2, %esi
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addw %bx, %ax
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adcl $0, %eax
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2:
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movl %ecx, %edx
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shrl $5, %ecx
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jz 2f
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testl %esi, %esi
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1: movl (%esi), %ebx
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adcl %ebx, %eax
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movl 4(%esi), %ebx
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adcl %ebx, %eax
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movl 8(%esi), %ebx
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adcl %ebx, %eax
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movl 12(%esi), %ebx
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adcl %ebx, %eax
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movl 16(%esi), %ebx
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adcl %ebx, %eax
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movl 20(%esi), %ebx
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adcl %ebx, %eax
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movl 24(%esi), %ebx
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adcl %ebx, %eax
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movl 28(%esi), %ebx
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adcl %ebx, %eax
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lea 32(%esi), %esi
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dec %ecx
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jne 1b
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adcl $0, %eax
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2: movl %edx, %ecx
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andl $0x1c, %edx
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je 4f
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shrl $2, %edx # This clears CF
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3: adcl (%esi), %eax
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lea 4(%esi), %esi
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dec %edx
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jne 3b
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adcl $0, %eax
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4: andl $3, %ecx
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jz 7f
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cmpl $2, %ecx
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jb 5f
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movw (%esi),%cx
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leal 2(%esi),%esi
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je 6f
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shll $16,%ecx
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5: movb (%esi),%cl
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6: addl %ecx,%eax
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adcl $0, %eax
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7:
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testb $1, 12(%esp)
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jz 8f
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roll $8, %eax
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8:
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popl_cfi_reg ebx
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popl_cfi_reg esi
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ret
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CFI_ENDPROC
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ENDPROC(csum_partial)
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#else
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/* Version for PentiumII/PPro */
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ENTRY(csum_partial)
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CFI_STARTPROC
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pushl_cfi_reg esi
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pushl_cfi_reg ebx
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movl 20(%esp),%eax # Function arg: unsigned int sum
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movl 16(%esp),%ecx # Function arg: int len
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movl 12(%esp),%esi # Function arg: const unsigned char *buf
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testl $3, %esi
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jnz 25f
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10:
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movl %ecx, %edx
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movl %ecx, %ebx
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andl $0x7c, %ebx
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shrl $7, %ecx
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addl %ebx,%esi
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shrl $2, %ebx
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negl %ebx
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lea 45f(%ebx,%ebx,2), %ebx
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testl %esi, %esi
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jmp *%ebx
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# Handle 2-byte-aligned regions
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20: addw (%esi), %ax
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lea 2(%esi), %esi
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adcl $0, %eax
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jmp 10b
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25:
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testl $1, %esi
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jz 30f
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# buf is odd
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dec %ecx
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jl 90f
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movzbl (%esi), %ebx
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addl %ebx, %eax
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adcl $0, %eax
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roll $8, %eax
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inc %esi
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testl $2, %esi
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jz 10b
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30: subl $2, %ecx
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ja 20b
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je 32f
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addl $2, %ecx
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jz 80f
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movzbl (%esi),%ebx # csumming 1 byte, 2-aligned
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addl %ebx, %eax
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adcl $0, %eax
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jmp 80f
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32:
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addw (%esi), %ax # csumming 2 bytes, 2-aligned
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adcl $0, %eax
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jmp 80f
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40:
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addl -128(%esi), %eax
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adcl -124(%esi), %eax
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adcl -120(%esi), %eax
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adcl -116(%esi), %eax
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adcl -112(%esi), %eax
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adcl -108(%esi), %eax
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adcl -104(%esi), %eax
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adcl -100(%esi), %eax
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adcl -96(%esi), %eax
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adcl -92(%esi), %eax
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adcl -88(%esi), %eax
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adcl -84(%esi), %eax
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adcl -80(%esi), %eax
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adcl -76(%esi), %eax
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adcl -72(%esi), %eax
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adcl -68(%esi), %eax
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adcl -64(%esi), %eax
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adcl -60(%esi), %eax
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adcl -56(%esi), %eax
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adcl -52(%esi), %eax
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adcl -48(%esi), %eax
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adcl -44(%esi), %eax
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adcl -40(%esi), %eax
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adcl -36(%esi), %eax
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adcl -32(%esi), %eax
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adcl -28(%esi), %eax
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adcl -24(%esi), %eax
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adcl -20(%esi), %eax
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adcl -16(%esi), %eax
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adcl -12(%esi), %eax
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adcl -8(%esi), %eax
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adcl -4(%esi), %eax
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45:
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lea 128(%esi), %esi
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adcl $0, %eax
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dec %ecx
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jge 40b
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movl %edx, %ecx
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50: andl $3, %ecx
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jz 80f
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# Handle the last 1-3 bytes without jumping
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notl %ecx # 1->2, 2->1, 3->0, higher bits are masked
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movl $0xffffff,%ebx # by the shll and shrl instructions
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shll $3,%ecx
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shrl %cl,%ebx
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andl -128(%esi),%ebx # esi is 4-aligned so should be ok
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addl %ebx,%eax
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adcl $0,%eax
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80:
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testb $1, 12(%esp)
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jz 90f
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roll $8, %eax
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90:
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popl_cfi_reg ebx
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popl_cfi_reg esi
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ret
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CFI_ENDPROC
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ENDPROC(csum_partial)
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#endif
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/*
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unsigned int csum_partial_copy_generic (const char *src, char *dst,
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int len, int sum, int *src_err_ptr, int *dst_err_ptr)
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*/
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/*
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* Copy from ds while checksumming, otherwise like csum_partial
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*
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* The macros SRC and DST specify the type of access for the instruction.
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* thus we can call a custom exception handler for all access types.
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*
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* FIXME: could someone double-check whether I haven't mixed up some SRC and
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* DST definitions? It's damn hard to trigger all cases. I hope I got
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* them all but there's no guarantee.
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*/
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#define SRC(y...) \
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9999: y; \
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_ASM_EXTABLE(9999b, 6001f)
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#define DST(y...) \
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9999: y; \
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_ASM_EXTABLE(9999b, 6002f)
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#ifndef CONFIG_X86_USE_PPRO_CHECKSUM
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#define ARGBASE 16
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#define FP 12
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ENTRY(csum_partial_copy_generic)
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CFI_STARTPROC
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subl $4,%esp
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CFI_ADJUST_CFA_OFFSET 4
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pushl_cfi_reg edi
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pushl_cfi_reg esi
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pushl_cfi_reg ebx
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movl ARGBASE+16(%esp),%eax # sum
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movl ARGBASE+12(%esp),%ecx # len
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movl ARGBASE+4(%esp),%esi # src
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movl ARGBASE+8(%esp),%edi # dst
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testl $2, %edi # Check alignment.
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jz 2f # Jump if alignment is ok.
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subl $2, %ecx # Alignment uses up two bytes.
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jae 1f # Jump if we had at least two bytes.
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addl $2, %ecx # ecx was < 2. Deal with it.
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jmp 4f
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SRC(1: movw (%esi), %bx )
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addl $2, %esi
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DST( movw %bx, (%edi) )
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addl $2, %edi
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addw %bx, %ax
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adcl $0, %eax
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2:
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movl %ecx, FP(%esp)
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shrl $5, %ecx
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jz 2f
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testl %esi, %esi
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SRC(1: movl (%esi), %ebx )
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SRC( movl 4(%esi), %edx )
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adcl %ebx, %eax
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DST( movl %ebx, (%edi) )
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adcl %edx, %eax
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DST( movl %edx, 4(%edi) )
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SRC( movl 8(%esi), %ebx )
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SRC( movl 12(%esi), %edx )
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adcl %ebx, %eax
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DST( movl %ebx, 8(%edi) )
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adcl %edx, %eax
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DST( movl %edx, 12(%edi) )
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SRC( movl 16(%esi), %ebx )
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SRC( movl 20(%esi), %edx )
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adcl %ebx, %eax
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DST( movl %ebx, 16(%edi) )
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adcl %edx, %eax
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DST( movl %edx, 20(%edi) )
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SRC( movl 24(%esi), %ebx )
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SRC( movl 28(%esi), %edx )
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adcl %ebx, %eax
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DST( movl %ebx, 24(%edi) )
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adcl %edx, %eax
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DST( movl %edx, 28(%edi) )
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lea 32(%esi), %esi
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lea 32(%edi), %edi
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dec %ecx
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jne 1b
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adcl $0, %eax
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2: movl FP(%esp), %edx
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movl %edx, %ecx
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andl $0x1c, %edx
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je 4f
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shrl $2, %edx # This clears CF
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SRC(3: movl (%esi), %ebx )
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adcl %ebx, %eax
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DST( movl %ebx, (%edi) )
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lea 4(%esi), %esi
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lea 4(%edi), %edi
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dec %edx
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jne 3b
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adcl $0, %eax
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4: andl $3, %ecx
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jz 7f
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cmpl $2, %ecx
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jb 5f
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SRC( movw (%esi), %cx )
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leal 2(%esi), %esi
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DST( movw %cx, (%edi) )
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leal 2(%edi), %edi
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je 6f
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shll $16,%ecx
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SRC(5: movb (%esi), %cl )
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DST( movb %cl, (%edi) )
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6: addl %ecx, %eax
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adcl $0, %eax
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7:
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5000:
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# Exception handler:
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.section .fixup, "ax"
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6001:
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movl ARGBASE+20(%esp), %ebx # src_err_ptr
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movl $-EFAULT, (%ebx)
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# zero the complete destination - computing the rest
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# is too much work
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movl ARGBASE+8(%esp), %edi # dst
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movl ARGBASE+12(%esp), %ecx # len
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xorl %eax,%eax
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rep ; stosb
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jmp 5000b
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6002:
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movl ARGBASE+24(%esp), %ebx # dst_err_ptr
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movl $-EFAULT,(%ebx)
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jmp 5000b
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.previous
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popl_cfi_reg ebx
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popl_cfi_reg esi
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popl_cfi_reg edi
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popl_cfi %ecx # equivalent to addl $4,%esp
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ret
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CFI_ENDPROC
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ENDPROC(csum_partial_copy_generic)
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#else
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/* Version for PentiumII/PPro */
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#define ROUND1(x) \
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SRC(movl x(%esi), %ebx ) ; \
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addl %ebx, %eax ; \
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DST(movl %ebx, x(%edi) ) ;
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#define ROUND(x) \
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SRC(movl x(%esi), %ebx ) ; \
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adcl %ebx, %eax ; \
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DST(movl %ebx, x(%edi) ) ;
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#define ARGBASE 12
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ENTRY(csum_partial_copy_generic)
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CFI_STARTPROC
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pushl_cfi_reg ebx
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pushl_cfi_reg edi
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pushl_cfi_reg esi
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movl ARGBASE+4(%esp),%esi #src
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movl ARGBASE+8(%esp),%edi #dst
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movl ARGBASE+12(%esp),%ecx #len
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movl ARGBASE+16(%esp),%eax #sum
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# movl %ecx, %edx
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movl %ecx, %ebx
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movl %esi, %edx
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|
shrl $6, %ecx
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|
andl $0x3c, %ebx
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|
negl %ebx
|
|
subl %ebx, %esi
|
|
subl %ebx, %edi
|
|
lea -1(%esi),%edx
|
|
andl $-32,%edx
|
|
lea 3f(%ebx,%ebx), %ebx
|
|
testl %esi, %esi
|
|
jmp *%ebx
|
|
1: addl $64,%esi
|
|
addl $64,%edi
|
|
SRC(movb -32(%edx),%bl) ; SRC(movb (%edx),%bl)
|
|
ROUND1(-64) ROUND(-60) ROUND(-56) ROUND(-52)
|
|
ROUND (-48) ROUND(-44) ROUND(-40) ROUND(-36)
|
|
ROUND (-32) ROUND(-28) ROUND(-24) ROUND(-20)
|
|
ROUND (-16) ROUND(-12) ROUND(-8) ROUND(-4)
|
|
3: adcl $0,%eax
|
|
addl $64, %edx
|
|
dec %ecx
|
|
jge 1b
|
|
4: movl ARGBASE+12(%esp),%edx #len
|
|
andl $3, %edx
|
|
jz 7f
|
|
cmpl $2, %edx
|
|
jb 5f
|
|
SRC( movw (%esi), %dx )
|
|
leal 2(%esi), %esi
|
|
DST( movw %dx, (%edi) )
|
|
leal 2(%edi), %edi
|
|
je 6f
|
|
shll $16,%edx
|
|
5:
|
|
SRC( movb (%esi), %dl )
|
|
DST( movb %dl, (%edi) )
|
|
6: addl %edx, %eax
|
|
adcl $0, %eax
|
|
7:
|
|
.section .fixup, "ax"
|
|
6001: movl ARGBASE+20(%esp), %ebx # src_err_ptr
|
|
movl $-EFAULT, (%ebx)
|
|
# zero the complete destination (computing the rest is too much work)
|
|
movl ARGBASE+8(%esp),%edi # dst
|
|
movl ARGBASE+12(%esp),%ecx # len
|
|
xorl %eax,%eax
|
|
rep; stosb
|
|
jmp 7b
|
|
6002: movl ARGBASE+24(%esp), %ebx # dst_err_ptr
|
|
movl $-EFAULT, (%ebx)
|
|
jmp 7b
|
|
.previous
|
|
|
|
popl_cfi_reg esi
|
|
popl_cfi_reg edi
|
|
popl_cfi_reg ebx
|
|
ret
|
|
CFI_ENDPROC
|
|
ENDPROC(csum_partial_copy_generic)
|
|
|
|
#undef ROUND
|
|
#undef ROUND1
|
|
|
|
#endif
|