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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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3e1aa7cb59
By the nature of the TEST operation, it is often possible to test
a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
This results in shorter instructions, because the TEST instruction
has no sign-entending byte-immediate forms unlike other ALU ops.
Note that this change does not create any LCP (Length-Changing Prefix)
stalls, which happen when adding a 0x66 prefix, which happens when
16-bit immediates are used, which changes such TEST instructions:
[test_opcode] [modrm] [imm32]
to:
[0x66] [test_opcode] [modrm] [imm16]
where [imm16] has a *different length* now: 2 bytes instead of 4.
This confuses the decoder and slows down execution.
REX prefixes were carefully designed to almost never hit this case:
adding REX prefix does not change instruction length except MOVABS
and MOV [addr],RAX instruction.
This patch does not add instructions which would use a 0x66 prefix,
code changes in assembly are:
-48 f7 07 01 00 00 00 testq $0x1,(%rdi)
+f6 07 01 testb $0x1,(%rdi)
-48 f7 c1 01 00 00 00 test $0x1,%rcx
+f6 c1 01 test $0x1,%cl
-48 f7 c1 02 00 00 00 test $0x2,%rcx
+f6 c1 02 test $0x2,%cl
-41 f7 c2 01 00 00 00 test $0x1,%r10d
+41 f6 c2 01 test $0x1,%r10b
-48 f7 c1 04 00 00 00 test $0x4,%rcx
+f6 c1 04 test $0x4,%cl
-48 f7 c1 08 00 00 00 test $0x8,%rcx
+f6 c1 08 test $0x8,%cl
Linus further notes:
"There are no stalls from using 8-bit instruction forms.
Now, changing from 64-bit or 32-bit 'test' instructions to 8-bit ones
*could* cause problems if it ends up having forwarding issues, so that
instead of just forwarding the result, you end up having to wait for
it to be stable in the L1 cache (or possibly the register file). The
forwarding from the store buffer is simplest and most reliable if the
read is done at the exact same address and the exact same size as the
write that gets forwarded.
But that's true only if:
(a) the write was very recent and is still in the write queue. I'm
not sure that's the case here anyway.
(b) on at least most Intel microarchitectures, you have to test a
different byte than the lowest one (so forwarding a 64-bit write
to a 8-bit read ends up working fine, as long as the 8-bit read
is of the low 8 bits of the written data).
A very similar issue *might* show up for registers too, not just
memory writes, if you use 'testb' with a high-byte register (where
instead of forwarding the value from the original producer it needs to
go through the register file and then shifted). But it's mainly a
problem for store buffers.
But afaik, the way Denys changed the test instructions, neither of the
above issues should be true.
The real problem for store buffer forwarding tends to be "write 8
bits, read 32 bits". That can be really surprisingly expensive,
because the read ends up having to wait until the write has hit the
cacheline, and we might talk tens of cycles of latency here. But
"write 32 bits, read the low 8 bits" *should* be fast on pretty much
all x86 chips, afaik."
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1425675332-31576-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
241 lines
4 KiB
ArmAsm
241 lines
4 KiB
ArmAsm
/*
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* Copyright 2002, 2003 Andi Kleen, SuSE Labs.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details. No warranty for anything given at all.
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*/
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#include <linux/linkage.h>
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#include <asm/dwarf2.h>
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#include <asm/errno.h>
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#include <asm/asm.h>
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/*
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* Checksum copy with exception handling.
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* On exceptions src_err_ptr or dst_err_ptr is set to -EFAULT and the
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* destination is zeroed.
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*
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* Input
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* rdi source
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* rsi destination
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* edx len (32bit)
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* ecx sum (32bit)
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* r8 src_err_ptr (int)
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* r9 dst_err_ptr (int)
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*
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* Output
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* eax 64bit sum. undefined in case of exception.
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*
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* Wrappers need to take care of valid exception sum and zeroing.
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* They also should align source or destination to 8 bytes.
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*/
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.macro source
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10:
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_ASM_EXTABLE(10b, .Lbad_source)
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.endm
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.macro dest
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20:
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_ASM_EXTABLE(20b, .Lbad_dest)
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.endm
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.macro ignore L=.Lignore
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30:
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_ASM_EXTABLE(30b, \L)
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.endm
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ENTRY(csum_partial_copy_generic)
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CFI_STARTPROC
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cmpl $3*64, %edx
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jle .Lignore
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.Lignore:
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subq $7*8, %rsp
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CFI_ADJUST_CFA_OFFSET 7*8
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movq %rbx, 2*8(%rsp)
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CFI_REL_OFFSET rbx, 2*8
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movq %r12, 3*8(%rsp)
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CFI_REL_OFFSET r12, 3*8
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movq %r14, 4*8(%rsp)
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CFI_REL_OFFSET r14, 4*8
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movq %r13, 5*8(%rsp)
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CFI_REL_OFFSET r13, 5*8
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movq %rbp, 6*8(%rsp)
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CFI_REL_OFFSET rbp, 6*8
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movq %r8, (%rsp)
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movq %r9, 1*8(%rsp)
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movl %ecx, %eax
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movl %edx, %ecx
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xorl %r9d, %r9d
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movq %rcx, %r12
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shrq $6, %r12
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jz .Lhandle_tail /* < 64 */
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clc
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/* main loop. clear in 64 byte blocks */
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/* r9: zero, r8: temp2, rbx: temp1, rax: sum, rcx: saved length */
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/* r11: temp3, rdx: temp4, r12 loopcnt */
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/* r10: temp5, rbp: temp6, r14 temp7, r13 temp8 */
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.p2align 4
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.Lloop:
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source
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movq (%rdi), %rbx
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source
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movq 8(%rdi), %r8
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source
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movq 16(%rdi), %r11
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source
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movq 24(%rdi), %rdx
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source
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movq 32(%rdi), %r10
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source
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movq 40(%rdi), %rbp
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source
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movq 48(%rdi), %r14
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source
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movq 56(%rdi), %r13
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ignore 2f
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prefetcht0 5*64(%rdi)
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2:
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adcq %rbx, %rax
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adcq %r8, %rax
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adcq %r11, %rax
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adcq %rdx, %rax
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adcq %r10, %rax
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adcq %rbp, %rax
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adcq %r14, %rax
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adcq %r13, %rax
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decl %r12d
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dest
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movq %rbx, (%rsi)
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dest
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movq %r8, 8(%rsi)
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dest
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movq %r11, 16(%rsi)
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dest
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movq %rdx, 24(%rsi)
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dest
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movq %r10, 32(%rsi)
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dest
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movq %rbp, 40(%rsi)
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dest
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movq %r14, 48(%rsi)
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dest
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movq %r13, 56(%rsi)
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3:
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leaq 64(%rdi), %rdi
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leaq 64(%rsi), %rsi
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jnz .Lloop
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adcq %r9, %rax
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/* do last up to 56 bytes */
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.Lhandle_tail:
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/* ecx: count */
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movl %ecx, %r10d
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andl $63, %ecx
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shrl $3, %ecx
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jz .Lfold
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clc
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.p2align 4
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.Lloop_8:
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source
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movq (%rdi), %rbx
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adcq %rbx, %rax
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decl %ecx
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dest
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movq %rbx, (%rsi)
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leaq 8(%rsi), %rsi /* preserve carry */
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leaq 8(%rdi), %rdi
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jnz .Lloop_8
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adcq %r9, %rax /* add in carry */
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.Lfold:
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/* reduce checksum to 32bits */
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movl %eax, %ebx
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shrq $32, %rax
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addl %ebx, %eax
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adcl %r9d, %eax
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/* do last up to 6 bytes */
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.Lhandle_7:
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movl %r10d, %ecx
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andl $7, %ecx
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shrl $1, %ecx
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jz .Lhandle_1
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movl $2, %edx
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xorl %ebx, %ebx
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clc
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.p2align 4
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.Lloop_1:
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source
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movw (%rdi), %bx
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adcl %ebx, %eax
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decl %ecx
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dest
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movw %bx, (%rsi)
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leaq 2(%rdi), %rdi
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leaq 2(%rsi), %rsi
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jnz .Lloop_1
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adcl %r9d, %eax /* add in carry */
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/* handle last odd byte */
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.Lhandle_1:
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testb $1, %r10b
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jz .Lende
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xorl %ebx, %ebx
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source
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movb (%rdi), %bl
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dest
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movb %bl, (%rsi)
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addl %ebx, %eax
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adcl %r9d, %eax /* carry */
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CFI_REMEMBER_STATE
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.Lende:
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movq 2*8(%rsp), %rbx
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CFI_RESTORE rbx
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movq 3*8(%rsp), %r12
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CFI_RESTORE r12
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movq 4*8(%rsp), %r14
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CFI_RESTORE r14
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movq 5*8(%rsp), %r13
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CFI_RESTORE r13
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movq 6*8(%rsp), %rbp
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CFI_RESTORE rbp
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addq $7*8, %rsp
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CFI_ADJUST_CFA_OFFSET -7*8
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ret
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CFI_RESTORE_STATE
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/* Exception handlers. Very simple, zeroing is done in the wrappers */
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.Lbad_source:
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movq (%rsp), %rax
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testq %rax, %rax
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jz .Lende
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movl $-EFAULT, (%rax)
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jmp .Lende
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.Lbad_dest:
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movq 8(%rsp), %rax
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testq %rax, %rax
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jz .Lende
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movl $-EFAULT, (%rax)
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jmp .Lende
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CFI_ENDPROC
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ENDPROC(csum_partial_copy_generic)
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