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![Meng Tang](/assets/img/avatar_default.png)
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypassed the hierarchical setup and messed up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by: Meng Tang <tangmeng@uniontech.com> Link: https://lore.kernel.org/r/20220225111929.17194-1-tangmeng@uniontech.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
375 lines
8.8 KiB
C
375 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Sound driver for Nintendo 64.
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*
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* Copyright 2021 Lauri Kasanen
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*/
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <sound/control.h>
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#include <sound/core.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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MODULE_AUTHOR("Lauri Kasanen <cand@gmx.com>");
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MODULE_DESCRIPTION("N64 Audio");
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MODULE_LICENSE("GPL");
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#define AI_NTSC_DACRATE 48681812
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#define AI_STATUS_BUSY (1 << 30)
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#define AI_STATUS_FULL (1 << 31)
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#define AI_ADDR_REG 0
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#define AI_LEN_REG 1
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#define AI_CONTROL_REG 2
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#define AI_STATUS_REG 3
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#define AI_RATE_REG 4
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#define AI_BITCLOCK_REG 5
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#define MI_INTR_REG 2
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#define MI_MASK_REG 3
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#define MI_INTR_AI 0x04
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#define MI_MASK_CLR_AI 0x0010
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#define MI_MASK_SET_AI 0x0020
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struct n64audio {
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u32 __iomem *ai_reg_base;
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u32 __iomem *mi_reg_base;
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void *ring_base;
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dma_addr_t ring_base_dma;
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struct snd_card *card;
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struct {
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struct snd_pcm_substream *substream;
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int pos, nextpos;
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u32 writesize;
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u32 bufsize;
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spinlock_t lock;
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} chan;
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};
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static void n64audio_write_reg(struct n64audio *priv, const u8 reg, const u32 value)
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{
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writel(value, priv->ai_reg_base + reg);
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}
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static void n64mi_write_reg(struct n64audio *priv, const u8 reg, const u32 value)
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{
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writel(value, priv->mi_reg_base + reg);
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}
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static u32 n64mi_read_reg(struct n64audio *priv, const u8 reg)
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{
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return readl(priv->mi_reg_base + reg);
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}
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static void n64audio_push(struct n64audio *priv)
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{
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struct snd_pcm_runtime *runtime = priv->chan.substream->runtime;
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unsigned long flags;
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u32 count;
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spin_lock_irqsave(&priv->chan.lock, flags);
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count = priv->chan.writesize;
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memcpy(priv->ring_base + priv->chan.nextpos,
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runtime->dma_area + priv->chan.nextpos, count);
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/*
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* The hw registers are double-buffered, and the IRQ fires essentially
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* one period behind. The core only allows one period's distance, so we
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* keep a private DMA buffer to afford two.
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*/
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n64audio_write_reg(priv, AI_ADDR_REG, priv->ring_base_dma + priv->chan.nextpos);
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barrier();
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n64audio_write_reg(priv, AI_LEN_REG, count);
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priv->chan.nextpos += count;
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priv->chan.nextpos %= priv->chan.bufsize;
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runtime->delay = runtime->period_size;
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spin_unlock_irqrestore(&priv->chan.lock, flags);
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}
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static irqreturn_t n64audio_isr(int irq, void *dev_id)
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{
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struct n64audio *priv = dev_id;
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const u32 intrs = n64mi_read_reg(priv, MI_INTR_REG);
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unsigned long flags;
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// Check it's ours
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if (!(intrs & MI_INTR_AI))
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return IRQ_NONE;
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n64audio_write_reg(priv, AI_STATUS_REG, 1);
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if (priv->chan.substream && snd_pcm_running(priv->chan.substream)) {
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spin_lock_irqsave(&priv->chan.lock, flags);
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priv->chan.pos = priv->chan.nextpos;
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spin_unlock_irqrestore(&priv->chan.lock, flags);
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snd_pcm_period_elapsed(priv->chan.substream);
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if (priv->chan.substream && snd_pcm_running(priv->chan.substream))
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n64audio_push(priv);
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}
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return IRQ_HANDLED;
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}
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static const struct snd_pcm_hardware n64audio_pcm_hw = {
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.info = (SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_BLOCK_TRANSFER),
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.formats = SNDRV_PCM_FMTBIT_S16_BE,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.rate_min = 8000,
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.rate_max = 48000,
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.channels_min = 2,
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.channels_max = 2,
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.buffer_bytes_max = 32768,
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.period_bytes_min = 1024,
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.period_bytes_max = 32768,
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.periods_min = 3,
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// 3 periods lets the double-buffering hw read one buffer behind safely
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.periods_max = 128,
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};
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static int hw_rule_period_size(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct snd_interval *c = hw_param_interval(params,
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SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
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int changed = 0;
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/*
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* The DMA unit has errata on (start + len) & 0x3fff == 0x2000.
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* This constraint makes sure that the period size is not a power of two,
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* which combined with dma_alloc_coherent aligning the buffer to the largest
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* PoT <= size guarantees it won't be hit.
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*/
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if (is_power_of_2(c->min)) {
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c->min += 2;
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changed = 1;
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}
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if (is_power_of_2(c->max)) {
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c->max -= 2;
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changed = 1;
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}
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if (snd_interval_checkempty(c)) {
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c->empty = 1;
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return -EINVAL;
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}
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return changed;
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}
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static int n64audio_pcm_open(struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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int err;
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runtime->hw = n64audio_pcm_hw;
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err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
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if (err < 0)
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return err;
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err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
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if (err < 0)
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return err;
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err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
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hw_rule_period_size, NULL, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
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if (err < 0)
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return err;
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return 0;
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}
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static int n64audio_pcm_prepare(struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct n64audio *priv = substream->pcm->private_data;
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u32 rate;
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rate = ((2 * AI_NTSC_DACRATE / runtime->rate) + 1) / 2 - 1;
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n64audio_write_reg(priv, AI_RATE_REG, rate);
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rate /= 66;
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if (rate > 16)
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rate = 16;
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n64audio_write_reg(priv, AI_BITCLOCK_REG, rate - 1);
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spin_lock_irq(&priv->chan.lock);
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/* Setup the pseudo-dma transfer pointers. */
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priv->chan.pos = 0;
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priv->chan.nextpos = 0;
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priv->chan.substream = substream;
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priv->chan.writesize = snd_pcm_lib_period_bytes(substream);
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priv->chan.bufsize = snd_pcm_lib_buffer_bytes(substream);
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spin_unlock_irq(&priv->chan.lock);
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return 0;
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}
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static int n64audio_pcm_trigger(struct snd_pcm_substream *substream,
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int cmd)
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{
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struct n64audio *priv = substream->pcm->private_data;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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n64audio_push(substream->pcm->private_data);
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n64audio_write_reg(priv, AI_CONTROL_REG, 1);
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n64mi_write_reg(priv, MI_MASK_REG, MI_MASK_SET_AI);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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n64audio_write_reg(priv, AI_CONTROL_REG, 0);
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n64mi_write_reg(priv, MI_MASK_REG, MI_MASK_CLR_AI);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static snd_pcm_uframes_t n64audio_pcm_pointer(struct snd_pcm_substream *substream)
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{
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struct n64audio *priv = substream->pcm->private_data;
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return bytes_to_frames(substream->runtime,
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priv->chan.pos);
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}
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static int n64audio_pcm_close(struct snd_pcm_substream *substream)
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{
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struct n64audio *priv = substream->pcm->private_data;
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priv->chan.substream = NULL;
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return 0;
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}
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static const struct snd_pcm_ops n64audio_pcm_ops = {
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.open = n64audio_pcm_open,
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.prepare = n64audio_pcm_prepare,
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.trigger = n64audio_pcm_trigger,
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.pointer = n64audio_pcm_pointer,
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.close = n64audio_pcm_close,
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};
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/*
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* The target device is embedded and RAM-constrained. We save RAM
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* by initializing in __init code that gets dropped late in boot.
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* For the same reason there is no module or unloading support.
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*/
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static int __init n64audio_probe(struct platform_device *pdev)
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{
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struct snd_card *card;
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struct snd_pcm *pcm;
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struct n64audio *priv;
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int err, irq;
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err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1,
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SNDRV_DEFAULT_STR1,
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THIS_MODULE, sizeof(*priv), &card);
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if (err < 0)
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return err;
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priv = card->private_data;
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spin_lock_init(&priv->chan.lock);
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priv->card = card;
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priv->ring_base = dma_alloc_coherent(card->dev, 32 * 1024, &priv->ring_base_dma,
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GFP_DMA|GFP_KERNEL);
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if (!priv->ring_base) {
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err = -ENOMEM;
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goto fail_card;
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}
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priv->mi_reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->mi_reg_base)) {
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err = PTR_ERR(priv->mi_reg_base);
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goto fail_dma_alloc;
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}
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priv->ai_reg_base = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(priv->ai_reg_base)) {
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err = PTR_ERR(priv->ai_reg_base);
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goto fail_dma_alloc;
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}
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err = snd_pcm_new(card, "N64 Audio", 0, 1, 0, &pcm);
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if (err < 0)
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goto fail_dma_alloc;
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pcm->private_data = priv;
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strcpy(pcm->name, "N64 Audio");
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snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &n64audio_pcm_ops);
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snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_VMALLOC, card->dev, 0, 0);
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strcpy(card->driver, "N64 Audio");
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strcpy(card->shortname, "N64 Audio");
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strcpy(card->longname, "N64 Audio");
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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err = -EINVAL;
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goto fail_dma_alloc;
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}
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if (devm_request_irq(&pdev->dev, irq, n64audio_isr,
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IRQF_SHARED, "N64 Audio", priv)) {
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err = -EBUSY;
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goto fail_dma_alloc;
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}
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err = snd_card_register(card);
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if (err < 0)
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goto fail_dma_alloc;
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return 0;
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fail_dma_alloc:
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dma_free_coherent(card->dev, 32 * 1024, priv->ring_base, priv->ring_base_dma);
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fail_card:
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snd_card_free(card);
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return err;
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}
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static struct platform_driver n64audio_driver = {
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.driver = {
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.name = "n64audio",
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},
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};
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static int __init n64audio_init(void)
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{
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return platform_driver_probe(&n64audio_driver, n64audio_probe);
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}
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module_init(n64audio_init);
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