Yifan Zha cf2c84d58c drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11 ... [ Upstream commit 97a3d6090f ] [Why] L1 blocks most of GC registers accessing by MMIO. [How] Use RLCG interface to program GC registers under SRIOV VF in full access time. Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-11-10 18:17:25 +01:00
..
drm	drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11	2022-11-10 18:17:25 +01:00
host1x	gpu: host1x: Use the bitmap API to allocate bitmaps	2022-07-08 17:38:34 +02:00
ipu-v3
trace
vga
Makefile