mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-14 06:35:12 +00:00
7edd7961e5
All the devices that make up the DRM device are now part of the same IOMMU group. This simplifies the handling of the IOMMU attachment and also avoids exhausting the number of IOMMUs available on early Tegra SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com>
401 lines
9.6 KiB
C
401 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Avionic Design GmbH
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* Copyright (C) 2013 NVIDIA Corporation
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*/
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#include <linux/clk.h>
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#include <linux/host1x.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <soc/tegra/pmc.h>
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#include "drm.h"
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#include "gem.h"
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#include "gr3d.h"
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struct gr3d_soc {
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unsigned int version;
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};
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struct gr3d {
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struct tegra_drm_client client;
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struct host1x_channel *channel;
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struct clk *clk_secondary;
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struct clk *clk;
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struct reset_control *rst_secondary;
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struct reset_control *rst;
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const struct gr3d_soc *soc;
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DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
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};
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static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
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{
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return container_of(client, struct gr3d, client);
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}
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static int gr3d_init(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->parent);
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unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
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struct gr3d *gr3d = to_gr3d(drm);
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int err;
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gr3d->channel = host1x_channel_request(client);
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if (!gr3d->channel)
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return -ENOMEM;
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client->syncpts[0] = host1x_syncpt_request(client, flags);
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if (!client->syncpts[0]) {
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err = -ENOMEM;
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dev_err(client->dev, "failed to request syncpoint: %d\n", err);
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goto put;
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}
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err = host1x_client_iommu_attach(client);
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if (err < 0) {
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dev_err(client->dev, "failed to attach to domain: %d\n", err);
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goto free;
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}
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err = tegra_drm_register_client(dev->dev_private, drm);
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if (err < 0) {
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dev_err(client->dev, "failed to register client: %d\n", err);
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goto detach;
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}
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return 0;
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detach:
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host1x_client_iommu_detach(client);
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free:
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host1x_syncpt_free(client->syncpts[0]);
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put:
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host1x_channel_put(gr3d->channel);
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return err;
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}
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static int gr3d_exit(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->parent);
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struct gr3d *gr3d = to_gr3d(drm);
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int err;
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err = tegra_drm_unregister_client(dev->dev_private, drm);
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if (err < 0)
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return err;
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host1x_client_iommu_detach(client);
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host1x_syncpt_free(client->syncpts[0]);
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host1x_channel_put(gr3d->channel);
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return 0;
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}
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static const struct host1x_client_ops gr3d_client_ops = {
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.init = gr3d_init,
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.exit = gr3d_exit,
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};
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static int gr3d_open_channel(struct tegra_drm_client *client,
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struct tegra_drm_context *context)
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{
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struct gr3d *gr3d = to_gr3d(client);
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context->channel = host1x_channel_get(gr3d->channel);
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if (!context->channel)
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return -ENOMEM;
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return 0;
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}
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static void gr3d_close_channel(struct tegra_drm_context *context)
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{
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host1x_channel_put(context->channel);
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}
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static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
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{
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struct gr3d *gr3d = dev_get_drvdata(dev);
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switch (class) {
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case HOST1X_CLASS_HOST1X:
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if (offset == 0x2b)
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return 1;
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break;
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case HOST1X_CLASS_GR3D:
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if (offset >= GR3D_NUM_REGS)
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break;
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if (test_bit(offset, gr3d->addr_regs))
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return 1;
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break;
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}
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return 0;
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}
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static const struct tegra_drm_client_ops gr3d_ops = {
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.open_channel = gr3d_open_channel,
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.close_channel = gr3d_close_channel,
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.is_addr_reg = gr3d_is_addr_reg,
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.submit = tegra_drm_submit,
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};
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static const struct gr3d_soc tegra20_gr3d_soc = {
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.version = 0x20,
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};
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static const struct gr3d_soc tegra30_gr3d_soc = {
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.version = 0x30,
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};
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static const struct gr3d_soc tegra114_gr3d_soc = {
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.version = 0x35,
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};
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static const struct of_device_id tegra_gr3d_match[] = {
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{ .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc },
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{ .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc },
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{ .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra_gr3d_match);
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static const u32 gr3d_addr_regs[] = {
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GR3D_IDX_ATTRIBUTE( 0),
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GR3D_IDX_ATTRIBUTE( 1),
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GR3D_IDX_ATTRIBUTE( 2),
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GR3D_IDX_ATTRIBUTE( 3),
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GR3D_IDX_ATTRIBUTE( 4),
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GR3D_IDX_ATTRIBUTE( 5),
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GR3D_IDX_ATTRIBUTE( 6),
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GR3D_IDX_ATTRIBUTE( 7),
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GR3D_IDX_ATTRIBUTE( 8),
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GR3D_IDX_ATTRIBUTE( 9),
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GR3D_IDX_ATTRIBUTE(10),
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GR3D_IDX_ATTRIBUTE(11),
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GR3D_IDX_ATTRIBUTE(12),
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GR3D_IDX_ATTRIBUTE(13),
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GR3D_IDX_ATTRIBUTE(14),
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GR3D_IDX_ATTRIBUTE(15),
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GR3D_IDX_INDEX_BASE,
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GR3D_QR_ZTAG_ADDR,
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GR3D_QR_CTAG_ADDR,
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GR3D_QR_CZ_ADDR,
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GR3D_TEX_TEX_ADDR( 0),
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GR3D_TEX_TEX_ADDR( 1),
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GR3D_TEX_TEX_ADDR( 2),
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GR3D_TEX_TEX_ADDR( 3),
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GR3D_TEX_TEX_ADDR( 4),
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GR3D_TEX_TEX_ADDR( 5),
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GR3D_TEX_TEX_ADDR( 6),
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GR3D_TEX_TEX_ADDR( 7),
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GR3D_TEX_TEX_ADDR( 8),
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GR3D_TEX_TEX_ADDR( 9),
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GR3D_TEX_TEX_ADDR(10),
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GR3D_TEX_TEX_ADDR(11),
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GR3D_TEX_TEX_ADDR(12),
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GR3D_TEX_TEX_ADDR(13),
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GR3D_TEX_TEX_ADDR(14),
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GR3D_TEX_TEX_ADDR(15),
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GR3D_DW_MEMORY_OUTPUT_ADDRESS,
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GR3D_GLOBAL_SURFADDR( 0),
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GR3D_GLOBAL_SURFADDR( 1),
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GR3D_GLOBAL_SURFADDR( 2),
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GR3D_GLOBAL_SURFADDR( 3),
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GR3D_GLOBAL_SURFADDR( 4),
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GR3D_GLOBAL_SURFADDR( 5),
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GR3D_GLOBAL_SURFADDR( 6),
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GR3D_GLOBAL_SURFADDR( 7),
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GR3D_GLOBAL_SURFADDR( 8),
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GR3D_GLOBAL_SURFADDR( 9),
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GR3D_GLOBAL_SURFADDR(10),
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GR3D_GLOBAL_SURFADDR(11),
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GR3D_GLOBAL_SURFADDR(12),
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GR3D_GLOBAL_SURFADDR(13),
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GR3D_GLOBAL_SURFADDR(14),
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GR3D_GLOBAL_SURFADDR(15),
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GR3D_GLOBAL_SPILLSURFADDR,
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GR3D_GLOBAL_SURFOVERADDR( 0),
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GR3D_GLOBAL_SURFOVERADDR( 1),
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GR3D_GLOBAL_SURFOVERADDR( 2),
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GR3D_GLOBAL_SURFOVERADDR( 3),
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GR3D_GLOBAL_SURFOVERADDR( 4),
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GR3D_GLOBAL_SURFOVERADDR( 5),
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GR3D_GLOBAL_SURFOVERADDR( 6),
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GR3D_GLOBAL_SURFOVERADDR( 7),
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GR3D_GLOBAL_SURFOVERADDR( 8),
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GR3D_GLOBAL_SURFOVERADDR( 9),
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GR3D_GLOBAL_SURFOVERADDR(10),
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GR3D_GLOBAL_SURFOVERADDR(11),
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GR3D_GLOBAL_SURFOVERADDR(12),
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GR3D_GLOBAL_SURFOVERADDR(13),
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GR3D_GLOBAL_SURFOVERADDR(14),
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GR3D_GLOBAL_SURFOVERADDR(15),
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GR3D_GLOBAL_SAMP01SURFADDR( 0),
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GR3D_GLOBAL_SAMP01SURFADDR( 1),
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GR3D_GLOBAL_SAMP01SURFADDR( 2),
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GR3D_GLOBAL_SAMP01SURFADDR( 3),
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GR3D_GLOBAL_SAMP01SURFADDR( 4),
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GR3D_GLOBAL_SAMP01SURFADDR( 5),
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GR3D_GLOBAL_SAMP01SURFADDR( 6),
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GR3D_GLOBAL_SAMP01SURFADDR( 7),
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GR3D_GLOBAL_SAMP01SURFADDR( 8),
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GR3D_GLOBAL_SAMP01SURFADDR( 9),
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GR3D_GLOBAL_SAMP01SURFADDR(10),
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GR3D_GLOBAL_SAMP01SURFADDR(11),
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GR3D_GLOBAL_SAMP01SURFADDR(12),
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GR3D_GLOBAL_SAMP01SURFADDR(13),
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GR3D_GLOBAL_SAMP01SURFADDR(14),
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GR3D_GLOBAL_SAMP01SURFADDR(15),
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GR3D_GLOBAL_SAMP23SURFADDR( 0),
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GR3D_GLOBAL_SAMP23SURFADDR( 1),
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GR3D_GLOBAL_SAMP23SURFADDR( 2),
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GR3D_GLOBAL_SAMP23SURFADDR( 3),
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GR3D_GLOBAL_SAMP23SURFADDR( 4),
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GR3D_GLOBAL_SAMP23SURFADDR( 5),
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GR3D_GLOBAL_SAMP23SURFADDR( 6),
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GR3D_GLOBAL_SAMP23SURFADDR( 7),
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GR3D_GLOBAL_SAMP23SURFADDR( 8),
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GR3D_GLOBAL_SAMP23SURFADDR( 9),
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GR3D_GLOBAL_SAMP23SURFADDR(10),
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GR3D_GLOBAL_SAMP23SURFADDR(11),
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GR3D_GLOBAL_SAMP23SURFADDR(12),
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GR3D_GLOBAL_SAMP23SURFADDR(13),
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GR3D_GLOBAL_SAMP23SURFADDR(14),
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GR3D_GLOBAL_SAMP23SURFADDR(15),
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};
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static int gr3d_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct host1x_syncpt **syncpts;
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struct gr3d *gr3d;
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unsigned int i;
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int err;
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gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
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if (!gr3d)
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return -ENOMEM;
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gr3d->soc = of_device_get_match_data(&pdev->dev);
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syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
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if (!syncpts)
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return -ENOMEM;
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gr3d->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(gr3d->clk)) {
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dev_err(&pdev->dev, "cannot get clock\n");
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return PTR_ERR(gr3d->clk);
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}
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gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
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if (IS_ERR(gr3d->rst)) {
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dev_err(&pdev->dev, "cannot get reset\n");
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return PTR_ERR(gr3d->rst);
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}
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if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
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gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
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if (IS_ERR(gr3d->clk_secondary)) {
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dev_err(&pdev->dev, "cannot get secondary clock\n");
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return PTR_ERR(gr3d->clk_secondary);
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}
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gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
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"3d2");
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if (IS_ERR(gr3d->rst_secondary)) {
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dev_err(&pdev->dev, "cannot get secondary reset\n");
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return PTR_ERR(gr3d->rst_secondary);
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}
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}
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
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gr3d->rst);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to power up 3D unit\n");
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return err;
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}
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if (gr3d->clk_secondary) {
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
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gr3d->clk_secondary,
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gr3d->rst_secondary);
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if (err < 0) {
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dev_err(&pdev->dev,
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"failed to power up secondary 3D unit\n");
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return err;
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}
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}
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INIT_LIST_HEAD(&gr3d->client.base.list);
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gr3d->client.base.ops = &gr3d_client_ops;
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gr3d->client.base.dev = &pdev->dev;
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gr3d->client.base.class = HOST1X_CLASS_GR3D;
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gr3d->client.base.syncpts = syncpts;
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gr3d->client.base.num_syncpts = 1;
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INIT_LIST_HEAD(&gr3d->client.list);
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gr3d->client.version = gr3d->soc->version;
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gr3d->client.ops = &gr3d_ops;
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err = host1x_client_register(&gr3d->client.base);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to register host1x client: %d\n",
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err);
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return err;
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}
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/* initialize address register map */
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for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
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set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
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platform_set_drvdata(pdev, gr3d);
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return 0;
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}
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static int gr3d_remove(struct platform_device *pdev)
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{
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struct gr3d *gr3d = platform_get_drvdata(pdev);
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int err;
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err = host1x_client_unregister(&gr3d->client.base);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
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err);
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return err;
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}
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if (gr3d->clk_secondary) {
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tegra_powergate_power_off(TEGRA_POWERGATE_3D1);
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clk_disable_unprepare(gr3d->clk_secondary);
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}
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tegra_powergate_power_off(TEGRA_POWERGATE_3D);
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clk_disable_unprepare(gr3d->clk);
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return 0;
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}
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struct platform_driver tegra_gr3d_driver = {
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.driver = {
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.name = "tegra-gr3d",
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.of_match_table = tegra_gr3d_match,
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},
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.probe = gr3d_probe,
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.remove = gr3d_remove,
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};
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