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![Stephen Boyd](/assets/img/avatar_default.png)
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
390 lines
8.5 KiB
C
390 lines
8.5 KiB
C
/*
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* Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
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* Copyright (C) 2015 Linaro Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/cpu.h>
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/topology.h>
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#include <linux/mailbox_client.h>
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#include <linux/platform_device.h>
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#include <soc/mb86s7x/scb_mhu.h>
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#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
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#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
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struct mb86s7x_peri_clk {
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u32 payload_size;
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u32 cntrlr;
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u32 domain;
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u32 port;
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u32 en;
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u64 frequency;
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} __packed __aligned(4);
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struct hack_rate {
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unsigned clk_id;
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unsigned long rate;
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int gated;
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};
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struct crg_clk {
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struct clk_hw hw;
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u8 cntrlr, domain, port;
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};
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static int crg_gate_control(struct clk_hw *hw, int en)
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{
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struct crg_clk *crgclk = to_crg_clk(hw);
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struct mb86s7x_peri_clk cmd;
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int ret;
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cmd.payload_size = sizeof(cmd);
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cmd.cntrlr = crgclk->cntrlr;
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cmd.domain = crgclk->domain;
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cmd.port = crgclk->port;
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cmd.en = en;
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/* Port is UngatedCLK */
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if (cmd.port == 8)
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return en ? 0 : -EINVAL;
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pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
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__func__, __LINE__, cmd.cntrlr,
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cmd.domain, cmd.port, cmd.en);
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ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
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&cmd, sizeof(cmd));
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if (ret < 0) {
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pr_err("%s:%d failed!\n", __func__, __LINE__);
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return ret;
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}
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pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
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__func__, __LINE__, cmd.cntrlr,
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cmd.domain, cmd.port, cmd.en);
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/* If the request was rejected */
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if (cmd.en != en)
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ret = -EINVAL;
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else
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ret = 0;
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return ret;
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}
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static int crg_port_prepare(struct clk_hw *hw)
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{
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return crg_gate_control(hw, 1);
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}
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static void crg_port_unprepare(struct clk_hw *hw)
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{
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crg_gate_control(hw, 0);
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}
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static int
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crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
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{
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struct crg_clk *crgclk = to_crg_clk(hw);
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struct mb86s7x_peri_clk cmd;
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int code, ret;
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cmd.payload_size = sizeof(cmd);
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cmd.cntrlr = crgclk->cntrlr;
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cmd.domain = crgclk->domain;
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cmd.port = crgclk->port;
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cmd.frequency = *rate;
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if (set) {
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code = CMD_PERI_CLOCK_RATE_SET_REQ;
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pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
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__func__, __LINE__, cmd.cntrlr,
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cmd.domain, cmd.port, cmd.frequency);
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} else {
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code = CMD_PERI_CLOCK_RATE_GET_REQ;
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pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
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__func__, __LINE__, cmd.cntrlr,
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cmd.domain, cmd.port);
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}
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ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
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if (ret < 0) {
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pr_err("%s:%d failed!\n", __func__, __LINE__);
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return ret;
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}
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if (set)
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pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
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__func__, __LINE__, cmd.cntrlr,
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cmd.domain, cmd.port, cmd.frequency);
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else
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pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
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__func__, __LINE__, cmd.cntrlr,
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cmd.domain, cmd.port, cmd.frequency);
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*rate = cmd.frequency;
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return 0;
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}
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static unsigned long
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crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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unsigned long rate;
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crg_rate_control(hw, 0, &rate);
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return rate;
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}
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static long
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crg_port_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *pr)
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{
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return rate;
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}
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static int
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crg_port_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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return crg_rate_control(hw, 1, &rate);
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}
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const struct clk_ops crg_port_ops = {
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.prepare = crg_port_prepare,
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.unprepare = crg_port_unprepare,
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.recalc_rate = crg_port_recalc_rate,
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.round_rate = crg_port_round_rate,
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.set_rate = crg_port_set_rate,
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};
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struct mb86s70_crg11 {
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struct mutex lock; /* protects CLK populating and searching */
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};
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static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
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{
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struct mb86s70_crg11 *crg11 = data;
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struct clk_init_data init;
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u32 cntrlr, domain, port;
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struct crg_clk *crgclk;
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struct clk *clk;
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char clkp[20];
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if (clkspec->args_count != 3)
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return ERR_PTR(-EINVAL);
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cntrlr = clkspec->args[0];
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domain = clkspec->args[1];
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port = clkspec->args[2];
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if (port > 7)
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snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
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else
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snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
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mutex_lock(&crg11->lock);
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clk = __clk_lookup(clkp);
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if (clk) {
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mutex_unlock(&crg11->lock);
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return clk;
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}
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crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
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if (!crgclk) {
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mutex_unlock(&crg11->lock);
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return ERR_PTR(-ENOMEM);
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}
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init.name = clkp;
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init.num_parents = 0;
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init.ops = &crg_port_ops;
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init.flags = 0;
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crgclk->hw.init = &init;
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crgclk->cntrlr = cntrlr;
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crgclk->domain = domain;
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crgclk->port = port;
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clk = clk_register(NULL, &crgclk->hw);
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if (IS_ERR(clk))
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pr_err("%s:%d Error!\n", __func__, __LINE__);
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else
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pr_debug("Registered %s\n", clkp);
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clk_register_clkdev(clk, clkp, NULL);
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mutex_unlock(&crg11->lock);
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return clk;
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}
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static void __init crg_port_init(struct device_node *node)
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{
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struct mb86s70_crg11 *crg11;
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crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
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if (!crg11)
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return;
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mutex_init(&crg11->lock);
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of_clk_add_provider(node, crg11_get, crg11);
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}
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CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
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struct cl_clk {
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struct clk_hw hw;
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int cluster;
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};
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struct mb86s7x_cpu_freq {
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u32 payload_size;
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u32 cluster_class;
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u32 cluster_id;
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u32 cpu_id;
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u64 frequency;
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};
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static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
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{
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struct cl_clk *clc = to_clc_clk(hw);
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struct mb86s7x_cpu_freq cmd;
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int code, ret;
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cmd.payload_size = sizeof(cmd);
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cmd.cluster_class = 0;
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cmd.cluster_id = clc->cluster;
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cmd.cpu_id = 0;
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cmd.frequency = *rate;
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if (get)
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code = CMD_CPU_CLOCK_RATE_GET_REQ;
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else
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code = CMD_CPU_CLOCK_RATE_SET_REQ;
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pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
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__func__, __LINE__, cmd.cluster_class,
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cmd.cluster_id, cmd.cpu_id, cmd.frequency);
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ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
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if (ret < 0) {
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pr_err("%s:%d failed!\n", __func__, __LINE__);
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return;
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}
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pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
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__func__, __LINE__, cmd.cluster_class,
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cmd.cluster_id, cmd.cpu_id, cmd.frequency);
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*rate = cmd.frequency;
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}
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static unsigned long
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clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
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{
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unsigned long rate;
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mhu_cluster_rate(hw, &rate, 1);
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return rate;
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}
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static long
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clc_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *unused)
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{
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return rate;
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}
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static int
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clc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long unused)
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{
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unsigned long res = rate;
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mhu_cluster_rate(hw, &res, 0);
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return (res == rate) ? 0 : -EINVAL;
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}
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static struct clk_ops clk_clc_ops = {
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.recalc_rate = clc_recalc_rate,
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.round_rate = clc_round_rate,
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.set_rate = clc_set_rate,
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};
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static struct clk_hw *mb86s7x_clclk_register(struct device *cpu_dev)
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{
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struct clk_init_data init;
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struct cl_clk *clc;
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int ret;
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clc = kzalloc(sizeof(*clc), GFP_KERNEL);
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if (!clc)
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return ERR_PTR(-ENOMEM);
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clc->hw.init = &init;
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clc->cluster = topology_physical_package_id(cpu_dev->id);
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init.name = dev_name(cpu_dev);
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init.ops = &clk_clc_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.num_parents = 0;
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ret = devm_clk_hw_register(cpu_dev, &clc->hw);
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if (ret)
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return ERR_PTR(ret);
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return &clc->hw;
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}
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static int mb86s7x_clclk_of_init(void)
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{
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int cpu, ret = -ENODEV;
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struct device_node *np;
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struct clk_hw *hw;
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np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
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if (!np || !of_device_is_available(np))
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goto exit;
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for_each_possible_cpu(cpu) {
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struct device *cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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pr_err("failed to get cpu%d device\n", cpu);
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continue;
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}
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hw = mb86s7x_clclk_register(cpu_dev);
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if (IS_ERR(hw)) {
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pr_err("failed to register cpu%d clock\n", cpu);
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continue;
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}
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if (clk_hw_register_clkdev(hw, NULL, dev_name(cpu_dev))) {
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pr_err("failed to register cpu%d clock lookup\n", cpu);
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continue;
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}
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pr_debug("registered clk for %s\n", dev_name(cpu_dev));
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}
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ret = 0;
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platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
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exit:
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of_node_put(np);
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return ret;
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}
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module_init(mb86s7x_clclk_of_init);
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