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![Axel Lin](/assets/img/avatar_default.png)
Return proper error in brcmstb_gpio_probe if bank width is invalid. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
551 lines
15 KiB
C
551 lines
15 KiB
C
/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/module.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#define GIO_BANK_SIZE 0x20
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#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
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#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
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#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
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#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
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#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
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#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
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#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
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#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
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struct brcmstb_gpio_bank {
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struct list_head node;
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int id;
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struct gpio_chip gc;
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struct brcmstb_gpio_priv *parent_priv;
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u32 width;
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struct irq_chip irq_chip;
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};
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struct brcmstb_gpio_priv {
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struct list_head bank_list;
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void __iomem *reg_base;
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struct platform_device *pdev;
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int parent_irq;
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int gpio_base;
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bool can_wake;
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int parent_wake_irq;
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struct notifier_block reboot_notifier;
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};
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#define MAX_GPIO_PER_BANK 32
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#define GPIO_BANK(gpio) ((gpio) >> 5)
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/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
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#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
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static inline struct brcmstb_gpio_priv *
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brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
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{
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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return bank->parent_priv;
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}
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static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
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unsigned int offset, bool enable)
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{
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struct gpio_chip *gc = &bank->gc;
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = gc->pin2mask(gc, offset);
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u32 imask;
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
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if (enable)
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imask |= mask;
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else
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imask &= ~mask;
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gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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/* -------------------- IRQ chip functions -------------------- */
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static void brcmstb_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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brcmstb_gpio_set_imask(bank, d->hwirq, false);
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}
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static void brcmstb_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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brcmstb_gpio_set_imask(bank, d->hwirq, true);
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}
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static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(d->hwirq);
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u32 edge_insensitive, iedge_insensitive;
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u32 edge_config, iedge_config;
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u32 level, ilevel;
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unsigned long flags;
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switch (type) {
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case IRQ_TYPE_LEVEL_LOW:
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level = 0;
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edge_config = 0;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level = mask;
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edge_config = 0;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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level = 0;
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edge_config = 0;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_EDGE_RISING:
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level = 0;
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edge_config = mask;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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level = 0;
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edge_config = 0; /* don't care, but want known value */
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edge_insensitive = mask;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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iedge_config = bank->gc.read_reg(priv->reg_base +
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GIO_EC(bank->id)) & ~mask;
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iedge_insensitive = bank->gc.read_reg(priv->reg_base +
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GIO_EI(bank->id)) & ~mask;
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ilevel = bank->gc.read_reg(priv->reg_base +
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GIO_LEVEL(bank->id)) & ~mask;
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bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
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iedge_config | edge_config);
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bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
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iedge_insensitive | edge_insensitive);
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bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
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ilevel | level);
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spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return 0;
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}
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static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
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unsigned int enable)
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{
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int ret = 0;
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/*
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* Only enable wake IRQ once for however many hwirqs can wake
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* since they all use the same wake IRQ. Mask will be set
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* up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
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*/
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if (enable)
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ret = enable_irq_wake(priv->parent_wake_irq);
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else
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ret = disable_irq_wake(priv->parent_wake_irq);
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if (ret)
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dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
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enable ? "enable" : "disable");
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return ret;
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}
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static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
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return brcmstb_gpio_priv_set_wake(priv, enable);
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}
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static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
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{
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struct brcmstb_gpio_priv *priv = data;
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if (!priv || irq != priv->parent_wake_irq)
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return IRQ_NONE;
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pm_wakeup_event(&priv->pdev->dev, 0);
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return IRQ_HANDLED;
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}
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static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
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{
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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struct irq_domain *irq_domain = bank->gc.irqdomain;
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void __iomem *reg_base = priv->reg_base;
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unsigned long status;
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unsigned long flags;
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spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
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bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
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int bit;
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for_each_set_bit(bit, &status, 32) {
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u32 stat = bank->gc.read_reg(reg_base +
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GIO_STAT(bank->id));
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if (bit >= bank->width)
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dev_warn(&priv->pdev->dev,
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"IRQ for invalid GPIO (bank=%d, offset=%d)\n",
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bank->id, bit);
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bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
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stat | BIT(bit));
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generic_handle_irq(irq_find_mapping(irq_domain, bit));
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}
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}
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spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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}
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/* Each UPG GIO block has one IRQ for all banks */
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static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct brcmstb_gpio_bank *bank;
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/* Interrupts weren't properly cleared during probe */
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BUG_ON(!priv || !chip);
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chained_irq_enter(chip, desc);
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list_for_each_entry(bank, &priv->bank_list, node)
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brcmstb_gpio_irq_bank_handler(bank);
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chained_irq_exit(chip, desc);
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}
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static int brcmstb_gpio_reboot(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct brcmstb_gpio_priv *priv =
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container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
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/* Enable GPIO for S5 cold boot */
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if (action == SYS_POWER_OFF)
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brcmstb_gpio_priv_set_wake(priv, 1);
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return NOTIFY_DONE;
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}
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/* Make sure that the number of banks matches up between properties */
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static int brcmstb_gpio_sanity_check_banks(struct device *dev,
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struct device_node *np, struct resource *res)
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{
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int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
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int num_banks =
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of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
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if (res_num_banks != num_banks) {
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dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
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res_num_banks, num_banks);
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return -EINVAL;
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} else {
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return 0;
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}
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}
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static int brcmstb_gpio_remove(struct platform_device *pdev)
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{
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struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
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struct brcmstb_gpio_bank *bank;
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int ret = 0;
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if (!priv) {
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dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
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return -EFAULT;
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}
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/*
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* You can lose return values below, but we report all errors, and it's
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* more important to actually perform all of the steps.
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*/
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list_for_each_entry(bank, &priv->bank_list, node)
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gpiochip_remove(&bank->gc);
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if (priv->reboot_notifier.notifier_call) {
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ret = unregister_reboot_notifier(&priv->reboot_notifier);
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if (ret)
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dev_err(&pdev->dev,
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"failed to unregister reboot notifier\n");
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}
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return ret;
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}
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static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
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const struct of_phandle_args *gpiospec, u32 *flags)
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{
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struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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int offset;
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if (gc->of_gpio_n_cells != 2) {
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WARN_ON(1);
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return -EINVAL;
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}
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if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
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return -EINVAL;
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offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
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if (offset >= gc->ngpio || offset < 0)
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return -EINVAL;
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if (unlikely(offset >= bank->width)) {
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dev_warn_ratelimited(&priv->pdev->dev,
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"Received request for invalid GPIO offset %d\n",
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gpiospec->args[0]);
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}
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if (flags)
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*flags = gpiospec->args[1];
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return offset;
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}
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/* Before calling, must have bank->parent_irq set and gpiochip registered */
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static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
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struct brcmstb_gpio_bank *bank)
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{
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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bank->irq_chip.name = dev_name(dev);
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bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
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bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
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bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
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/* Ensures that all non-wakeup IRQs are disabled at suspend */
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bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
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of_property_read_bool(np, "wakeup-source")) {
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priv->parent_wake_irq = platform_get_irq(pdev, 1);
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if (priv->parent_wake_irq < 0) {
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dev_warn(dev,
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"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
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} else {
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int err;
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/*
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* Set wakeup capability before requesting wakeup
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* interrupt, so we can process boot-time "wakeups"
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* (e.g., from S5 cold boot)
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*/
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device_set_wakeup_capable(dev, true);
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device_wakeup_enable(dev);
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err = devm_request_irq(dev, priv->parent_wake_irq,
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brcmstb_gpio_wake_irq_handler, 0,
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"brcmstb-gpio-wake", priv);
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if (err < 0) {
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dev_err(dev, "Couldn't request wake IRQ");
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return err;
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}
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priv->reboot_notifier.notifier_call =
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brcmstb_gpio_reboot;
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register_reboot_notifier(&priv->reboot_notifier);
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priv->can_wake = true;
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}
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}
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if (priv->can_wake)
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bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
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gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
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handle_simple_irq, IRQ_TYPE_NONE);
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gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
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priv->parent_irq, brcmstb_gpio_irq_handler);
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return 0;
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}
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static int brcmstb_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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void __iomem *reg_base;
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struct brcmstb_gpio_priv *priv;
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struct resource *res;
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struct property *prop;
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const __be32 *p;
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u32 bank_width;
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int num_banks = 0;
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int err;
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static int gpio_base;
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unsigned long flags = 0;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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INIT_LIST_HEAD(&priv->bank_list);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(reg_base))
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return PTR_ERR(reg_base);
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priv->gpio_base = gpio_base;
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priv->reg_base = reg_base;
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priv->pdev = pdev;
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if (of_property_read_bool(np, "interrupt-controller")) {
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priv->parent_irq = platform_get_irq(pdev, 0);
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if (priv->parent_irq <= 0) {
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dev_err(dev, "Couldn't get IRQ");
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return -ENOENT;
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}
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} else {
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priv->parent_irq = -ENOENT;
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}
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if (brcmstb_gpio_sanity_check_banks(dev, np, res))
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return -EINVAL;
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/*
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* MIPS endianness is configured by boot strap, which also reverses all
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* bus endianness (i.e., big-endian CPU + big endian bus ==> native
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* endian I/O).
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*
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* Other architectures (e.g., ARM) either do not support big endian, or
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* else leave I/O in little endian mode.
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*/
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#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
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flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
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#endif
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of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
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bank_width) {
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struct brcmstb_gpio_bank *bank;
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struct gpio_chip *gc;
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bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
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if (!bank) {
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err = -ENOMEM;
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goto fail;
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}
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bank->parent_priv = priv;
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bank->id = num_banks;
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if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
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dev_err(dev, "Invalid bank width %d\n", bank_width);
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err = -EINVAL;
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goto fail;
|
|
} else {
|
|
bank->width = bank_width;
|
|
}
|
|
|
|
/*
|
|
* Regs are 4 bytes wide, have data reg, no set/clear regs,
|
|
* and direction bits have 0 = output and 1 = input
|
|
*/
|
|
gc = &bank->gc;
|
|
err = bgpio_init(gc, dev, 4,
|
|
reg_base + GIO_DATA(bank->id),
|
|
NULL, NULL, NULL,
|
|
reg_base + GIO_IODIR(bank->id), flags);
|
|
if (err) {
|
|
dev_err(dev, "bgpio_init() failed\n");
|
|
goto fail;
|
|
}
|
|
|
|
gc->of_node = np;
|
|
gc->owner = THIS_MODULE;
|
|
gc->label = np->full_name;
|
|
gc->base = gpio_base;
|
|
gc->of_gpio_n_cells = 2;
|
|
gc->of_xlate = brcmstb_gpio_of_xlate;
|
|
/* not all ngpio lines are valid, will use bank width later */
|
|
gc->ngpio = MAX_GPIO_PER_BANK;
|
|
|
|
/*
|
|
* Mask all interrupts by default, since wakeup interrupts may
|
|
* be retained from S5 cold boot
|
|
*/
|
|
gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
|
|
|
|
err = gpiochip_add_data(gc, bank);
|
|
if (err) {
|
|
dev_err(dev, "Could not add gpiochip for bank %d\n",
|
|
bank->id);
|
|
goto fail;
|
|
}
|
|
gpio_base += gc->ngpio;
|
|
|
|
if (priv->parent_irq > 0) {
|
|
err = brcmstb_gpio_irq_setup(pdev, bank);
|
|
if (err)
|
|
goto fail;
|
|
}
|
|
|
|
dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
|
|
gc->base, gc->ngpio, bank->width);
|
|
|
|
/* Everything looks good, so add bank to list */
|
|
list_add(&bank->node, &priv->bank_list);
|
|
|
|
num_banks++;
|
|
}
|
|
|
|
dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
|
|
num_banks, priv->gpio_base, gpio_base - 1);
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
(void) brcmstb_gpio_remove(pdev);
|
|
return err;
|
|
}
|
|
|
|
static const struct of_device_id brcmstb_gpio_of_match[] = {
|
|
{ .compatible = "brcm,brcmstb-gpio" },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
|
|
|
|
static struct platform_driver brcmstb_gpio_driver = {
|
|
.driver = {
|
|
.name = "brcmstb-gpio",
|
|
.of_match_table = brcmstb_gpio_of_match,
|
|
},
|
|
.probe = brcmstb_gpio_probe,
|
|
.remove = brcmstb_gpio_remove,
|
|
};
|
|
module_platform_driver(brcmstb_gpio_driver);
|
|
|
|
MODULE_AUTHOR("Gregory Fong");
|
|
MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
|
|
MODULE_LICENSE("GPL v2");
|