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![Linus Torvalds](/assets/img/avatar_default.png)
Subsystem improvements: - Do away with the last users of the obsolete Kconfig options ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB (the latter always sounded like an item on a wishlist to Santa Claus to me). We can now select GPIOLIB and be done with it, for all archs. After some struggle it even work on UM. Not that it has GPIO, but if it wants to, it can select the library. - Continued efforts to make drivers properly either tristate or bool. - Introduce a warning for drivers assigning default triggers to their irqchip lines when probed from device tree, so we find and fix these ambigous drivers. It is agreed that in the OF config path, the device tree defines trigger characteristics. - The same warning, mutatis mutandis, for ACPI-probed GPIO irqchips. - We introduce the ability to mark certain IRQ lines as "unusable" as they can be taken by BIOS/firmware, unrouted in silicon and generally nasty if you use them, and such things. This is put to good use in the STMPE driver and also in the Cherryview pin control driver. - A new "mockup" virtual GPIO device that can be used for testing. The plan is to add unit tests under tools/* for exercising this device and verify that the kernel code paths are working as they should. - Make memory-mapped I/O-drivers depend on HAS_IOMEM. This was implicit all the time, but when people started building UM with allyesconfig or allmodconfig it exploded in their face. - Move some stray bits of device tree and ACPI HW description callbacks down into their respective implementation silo. These were causing issues when compiling on !HAS_IOMEM as well, so now eventually UM compiles the GPIOLIB library if it wants to. New drivers: - New driver for the Aspeed GPIO front-end companion to the pin controller merged through the pin control tree. - New driver for the LP873x PMIC GPIO portions. - New driver for Technologic Systems' I2C FPGA GPIO such as TS4900, TS-7970, TS-7990 and TS-4100. - New driver for the Broadcom BCM63xx series including BCM6338 and BCM6345. - New driver for the Intel WhiskeyCove PMIC GPIO. - New driver for the Allwinner AXP209 PMIC GPIO portions. - New driver for Diamond Systems 48 line GPIO-MM, another of these port-mapped I/O expansion cards. - Support the STMicroelectronics STMPE1600 variant in the STMPE driver. Driver improvements: - The STMPE driver now supports rising/falling edge detection properly for IRQs. - The PCA954x will now fetch and enable its VCC regulator properly. - Major rework of the PCA953x driver with the goal of eventually switching it over to use regmap and thus modernize it even more. - Switch the IOP driver to use the generic MMIO GPIO library. - Move the ages old HTC EGPIO (extended GPIO) GPIO expander driver over to this subsystem from MFD, achieveing some separation of concerns. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJX9OvDAAoJEEEQszewGV1zsPQP/3VLy1fNIpMF0DDyq5tA/GNv sinnaPgMtt+qBrM2sbJcTVwV9xtHrs12CC3+2lAhBCIEm4YfHbXvaUMNE+aKJzk4 ZM7/rb8WMUxjQqzDKStdETsQGo6fxh0qU81OEQNbX9alir20jik9DvTufcs6xCgx sqh8KsNGO4Y6tiuKZ6mTZvIjVhMwiTm0NBSDKhdim0DdsOcuxyh6xVOj/0LB2Ei6 g75X1w++wjh0ryY3bzaeWkQSlXDC6eEKeez7VaEkSUyrxH86buomy0+aP0fqs7vY LRZzn/TC97YLT6hslS/OhB7uXrDIY2POSwO/SvusJcveGP7WPGyGr5mDtA4ATRWI ios0DBWl629kHfhAMzg3kPJS8LfjCerapvtbdAgqvhH+Vb5IPFx45vypDkR2WtJ7 bNAySIRMQSHZvJSCvYzjqh8AbWdE4i4k70tFXRMOpWeKIvRVI1cDvLD6cLn3hATM IPTytM6i2xqnzcq7mK7EJ18afcR0mv1jHgGAv4M0RMkyJ2IrURvFyZIvUB2MTyuL PEBh1ZvTs+MO50eeFwzltY91eagkzgWB0f6sm3l7I7bL2oxE2f/WVcVL9jWbgwpF otjFO27u0/6rIulfLUQzDo3gbOq7UaN0VTW4E9CYbOtFtNzCxjFIKTv0IJhTu4TT OSur7oFpzAMOGYlpYP8j =ABbi -----END PGP SIGNATURE----- Merge tag 'gpio-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.9 series: Subsystem improvements: - do away with the last users of the obsolete Kconfig options ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB (the latter always sounded like an item on a wishlist to Santa Claus to me). We can now select GPIOLIB and be done with it, for all archs. After some struggle it even work on UM. Not that it has GPIO, but if it wants to, it can select the library. - continued efforts to make drivers properly either tristate or bool. - introduce a warning for drivers assigning default triggers to their irqchip lines when probed from device tree, so we find and fix these ambigous drivers. It is agreed that in the OF config path, the device tree defines trigger characteristics. - the same warning, mutatis mutandis, for ACPI-probed GPIO irqchips. - we introduce the ability to mark certain IRQ lines as "unusable" as they can be taken by BIOS/firmware, unrouted in silicon and generally nasty if you use them, and such things. This is put to good use in the STMPE driver and also in the Cherryview pin control driver. - a new "mockup" virtual GPIO device that can be used for testing. The plan is to add unit tests under tools/* for exercising this device and verify that the kernel code paths are working as they should. - make memory-mapped I/O-drivers depend on HAS_IOMEM. This was implicit all the time, but when people started building UM with allyesconfig or allmodconfig it exploded in their face. - move some stray bits of device tree and ACPI HW description callbacks down into their respective implementation silo. These were causing issues when compiling on !HAS_IOMEM as well, so now eventually UM compiles the GPIOLIB library if it wants to. New drivers: - new driver for the Aspeed GPIO front-end companion to the pin controller merged through the pin control tree. - new driver for the LP873x PMIC GPIO portions. - new driver for Technologic Systems' I2C FPGA GPIO such as TS4900, TS-7970, TS-7990 and TS-4100. - new driver for the Broadcom BCM63xx series including BCM6338 and BCM6345. - new driver for the Intel WhiskeyCove PMIC GPIO. - new driver for the Allwinner AXP209 PMIC GPIO portions. - new driver for Diamond Systems 48 line GPIO-MM, another of these port-mapped I/O expansion cards. - support the STMicroelectronics STMPE1600 variant in the STMPE driver. Driver improvements: - the STMPE driver now supports rising/falling edge detection properly for IRQs. - the PCA954x will now fetch and enable its VCC regulator properly. - major rework of the PCA953x driver with the goal of eventually switching it over to use regmap and thus modernize it even more. - switch the IOP driver to use the generic MMIO GPIO library. - move the ages old HTC EGPIO (extended GPIO) GPIO expander driver over to this subsystem from MFD, achieveing some separation of concerns" * tag 'gpio-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (81 commits) gpio: add missing static inline gpio: OF: localize some gpiochip init functions gpio: acpi: separation of concerns gpio: OF: separation of concerns gpio: make memory-mapped drivers depend on HAS_IOMEM gpio: stmpe: use BIT() macro gpio: stmpe: forbid unused lines to be mapped as IRQs mfd/gpio: Move HTC GPIO driver to GPIO subsystem gpio: MAINTAINERS: Add an entry for GPIO mockup driver gpio/mockup: add virtual gpio device gpio: Added zynq specific check for special pins on bank zero gpio: axp209: Implement get_direction gpio: aspeed: remove redundant return value check gpio: loongson1: remove redundant return value check ARM: omap2: fix missing include gpio: tc3589x: fix up complaints on unsigned gpio: tc3589x: add .get_direction() and small cleanup gpio: f7188x: use gpiochip_get_data instead of container_of gpio: tps65218: use devm_gpiochip_add_data() for gpio registration gpio: aspeed: fix return value check in aspeed_gpio_probe() ...
518 lines
13 KiB
C
518 lines
13 KiB
C
/*
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* Based on code from Freescale Semiconductor,
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* Authors: Daniel Mack, Juergen Beisert.
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* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/gpio/driver.h>
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/* FIXME: for gpio_get_value() replace this with direct register read */
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#include <linux/gpio.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/bug.h>
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enum mxc_gpio_hwtype {
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IMX1_GPIO, /* runs on i.mx1 */
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IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
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IMX31_GPIO, /* runs on i.mx31 */
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IMX35_GPIO, /* runs on all other i.mx */
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};
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/* device type dependent stuff */
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struct mxc_gpio_hwdata {
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unsigned dr_reg;
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unsigned gdir_reg;
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unsigned psr_reg;
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unsigned icr1_reg;
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unsigned icr2_reg;
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unsigned imr_reg;
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unsigned isr_reg;
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int edge_sel_reg;
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unsigned low_level;
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unsigned high_level;
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unsigned rise_edge;
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unsigned fall_edge;
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};
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struct mxc_gpio_port {
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struct list_head node;
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void __iomem *base;
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int irq;
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int irq_high;
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struct irq_domain *domain;
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struct gpio_chip gc;
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u32 both_edges;
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};
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static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
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.dr_reg = 0x1c,
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.gdir_reg = 0x00,
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.psr_reg = 0x24,
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.icr1_reg = 0x28,
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.icr2_reg = 0x2c,
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.imr_reg = 0x30,
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.isr_reg = 0x34,
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.edge_sel_reg = -EINVAL,
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.low_level = 0x03,
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.high_level = 0x02,
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.rise_edge = 0x00,
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.fall_edge = 0x01,
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};
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static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
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.dr_reg = 0x00,
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.gdir_reg = 0x04,
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.psr_reg = 0x08,
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.icr1_reg = 0x0c,
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.icr2_reg = 0x10,
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.imr_reg = 0x14,
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.isr_reg = 0x18,
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.edge_sel_reg = -EINVAL,
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.low_level = 0x00,
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.high_level = 0x01,
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.rise_edge = 0x02,
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.fall_edge = 0x03,
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};
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static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
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.dr_reg = 0x00,
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.gdir_reg = 0x04,
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.psr_reg = 0x08,
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.icr1_reg = 0x0c,
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.icr2_reg = 0x10,
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.imr_reg = 0x14,
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.isr_reg = 0x18,
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.edge_sel_reg = 0x1c,
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.low_level = 0x00,
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.high_level = 0x01,
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.rise_edge = 0x02,
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.fall_edge = 0x03,
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};
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static enum mxc_gpio_hwtype mxc_gpio_hwtype;
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static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
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#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
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#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
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#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
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#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
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#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
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#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
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#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
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#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
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#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
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#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
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#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
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#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
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#define GPIO_INT_BOTH_EDGES 0x4
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static const struct platform_device_id mxc_gpio_devtype[] = {
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{
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.name = "imx1-gpio",
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.driver_data = IMX1_GPIO,
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}, {
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.name = "imx21-gpio",
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.driver_data = IMX21_GPIO,
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}, {
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.name = "imx31-gpio",
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.driver_data = IMX31_GPIO,
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}, {
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.name = "imx35-gpio",
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.driver_data = IMX35_GPIO,
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}, {
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/* sentinel */
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}
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};
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static const struct of_device_id mxc_gpio_dt_ids[] = {
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{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
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{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
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{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
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{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
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{ /* sentinel */ }
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};
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/*
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* MX2 has one interrupt *for all* gpio ports. The list is used
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* to save the references to all ports, so that mx2_gpio_irq_handler
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* can walk through all interrupt status registers.
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*/
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static LIST_HEAD(mxc_gpio_ports);
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/* Note: This driver assumes 32 GPIOs are handled in one register */
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static int gpio_set_irq_type(struct irq_data *d, u32 type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxc_gpio_port *port = gc->private;
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u32 bit, val;
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u32 gpio_idx = d->hwirq;
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u32 gpio = port->gc.base + gpio_idx;
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int edge;
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void __iomem *reg = port->base;
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port->both_edges &= ~(1 << gpio_idx);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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edge = GPIO_INT_RISE_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge = GPIO_INT_FALL_EDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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if (GPIO_EDGE_SEL >= 0) {
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edge = GPIO_INT_BOTH_EDGES;
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} else {
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val = gpio_get_value(gpio);
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if (val) {
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
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} else {
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
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}
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port->both_edges |= 1 << gpio_idx;
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}
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge = GPIO_INT_LOW_LEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge = GPIO_INT_HIGH_LEV;
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break;
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default:
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return -EINVAL;
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}
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if (GPIO_EDGE_SEL >= 0) {
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val = readl(port->base + GPIO_EDGE_SEL);
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if (edge == GPIO_INT_BOTH_EDGES)
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writel(val | (1 << gpio_idx),
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port->base + GPIO_EDGE_SEL);
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else
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writel(val & ~(1 << gpio_idx),
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port->base + GPIO_EDGE_SEL);
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}
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if (edge != GPIO_INT_BOTH_EDGES) {
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reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
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bit = gpio_idx & 0xf;
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val = readl(reg) & ~(0x3 << (bit << 1));
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writel(val | (edge << (bit << 1)), reg);
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}
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writel(1 << gpio_idx, port->base + GPIO_ISR);
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return 0;
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}
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static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
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{
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void __iomem *reg = port->base;
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u32 bit, val;
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int edge;
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reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
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bit = gpio & 0xf;
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val = readl(reg);
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edge = (val >> (bit << 1)) & 3;
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val &= ~(0x3 << (bit << 1));
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if (edge == GPIO_INT_HIGH_LEV) {
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
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} else if (edge == GPIO_INT_LOW_LEV) {
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
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} else {
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pr_err("mxc: invalid configuration for GPIO %d: %x\n",
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gpio, edge);
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return;
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}
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writel(val | (edge << (bit << 1)), reg);
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}
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/* handle 32 interrupts in one status register */
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static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
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{
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while (irq_stat != 0) {
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int irqoffset = fls(irq_stat) - 1;
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if (port->both_edges & (1 << irqoffset))
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mxc_flip_edge(port, irqoffset);
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generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
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irq_stat &= ~(1 << irqoffset);
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}
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}
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/* MX1 and MX3 has one interrupt *per* gpio port */
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static void mx3_gpio_irq_handler(struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
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mxc_gpio_irq_handler(port, irq_stat);
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chained_irq_exit(chip, desc);
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}
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/* MX2 has one interrupt *for all* gpio ports */
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static void mx2_gpio_irq_handler(struct irq_desc *desc)
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{
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u32 irq_msk, irq_stat;
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struct mxc_gpio_port *port;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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/* walk through all interrupt status registers */
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list_for_each_entry(port, &mxc_gpio_ports, node) {
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irq_msk = readl(port->base + GPIO_IMR);
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if (!irq_msk)
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continue;
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irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
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if (irq_stat)
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mxc_gpio_irq_handler(port, irq_stat);
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}
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chained_irq_exit(chip, desc);
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}
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/*
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* Set interrupt number "irq" in the GPIO as a wake-up source.
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* While system is running, all registered GPIO interrupts need to have
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* wake-up enabled. When system is suspended, only selected GPIO interrupts
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* need to have wake-up enabled.
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* @param irq interrupt source number
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* @param enable enable as wake-up if equal to non-zero
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* @return This function returns 0 on success.
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*/
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static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxc_gpio_port *port = gc->private;
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u32 gpio_idx = d->hwirq;
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if (enable) {
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if (port->irq_high && (gpio_idx >= 16))
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enable_irq_wake(port->irq_high);
|
|
else
|
|
enable_irq_wake(port->irq);
|
|
} else {
|
|
if (port->irq_high && (gpio_idx >= 16))
|
|
disable_irq_wake(port->irq_high);
|
|
else
|
|
disable_irq_wake(port->irq);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
|
|
{
|
|
struct irq_chip_generic *gc;
|
|
struct irq_chip_type *ct;
|
|
|
|
gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
|
|
port->base, handle_level_irq);
|
|
if (!gc)
|
|
return -ENOMEM;
|
|
gc->private = port;
|
|
|
|
ct = gc->chip_types;
|
|
ct->chip.irq_ack = irq_gc_ack_set_bit;
|
|
ct->chip.irq_mask = irq_gc_mask_clr_bit;
|
|
ct->chip.irq_unmask = irq_gc_mask_set_bit;
|
|
ct->chip.irq_set_type = gpio_set_irq_type;
|
|
ct->chip.irq_set_wake = gpio_set_wake_irq;
|
|
ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
|
|
ct->regs.ack = GPIO_ISR;
|
|
ct->regs.mask = GPIO_IMR;
|
|
|
|
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
|
|
IRQ_NOREQUEST, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mxc_gpio_get_hw(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id =
|
|
of_match_device(mxc_gpio_dt_ids, &pdev->dev);
|
|
enum mxc_gpio_hwtype hwtype;
|
|
|
|
if (of_id)
|
|
pdev->id_entry = of_id->data;
|
|
hwtype = pdev->id_entry->driver_data;
|
|
|
|
if (mxc_gpio_hwtype) {
|
|
/*
|
|
* The driver works with a reasonable presupposition,
|
|
* that is all gpio ports must be the same type when
|
|
* running on one soc.
|
|
*/
|
|
BUG_ON(mxc_gpio_hwtype != hwtype);
|
|
return;
|
|
}
|
|
|
|
if (hwtype == IMX35_GPIO)
|
|
mxc_gpio_hwdata = &imx35_gpio_hwdata;
|
|
else if (hwtype == IMX31_GPIO)
|
|
mxc_gpio_hwdata = &imx31_gpio_hwdata;
|
|
else
|
|
mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
|
|
|
|
mxc_gpio_hwtype = hwtype;
|
|
}
|
|
|
|
static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
|
|
{
|
|
struct mxc_gpio_port *port = gpiochip_get_data(gc);
|
|
|
|
return irq_find_mapping(port->domain, offset);
|
|
}
|
|
|
|
static int mxc_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct mxc_gpio_port *port;
|
|
struct resource *iores;
|
|
int irq_base;
|
|
int err;
|
|
|
|
mxc_gpio_get_hw(pdev);
|
|
|
|
port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
|
|
if (!port)
|
|
return -ENOMEM;
|
|
|
|
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
port->base = devm_ioremap_resource(&pdev->dev, iores);
|
|
if (IS_ERR(port->base))
|
|
return PTR_ERR(port->base);
|
|
|
|
port->irq_high = platform_get_irq(pdev, 1);
|
|
port->irq = platform_get_irq(pdev, 0);
|
|
if (port->irq < 0)
|
|
return port->irq;
|
|
|
|
/* disable the interrupt and clear the status */
|
|
writel(0, port->base + GPIO_IMR);
|
|
writel(~0, port->base + GPIO_ISR);
|
|
|
|
if (mxc_gpio_hwtype == IMX21_GPIO) {
|
|
/*
|
|
* Setup one handler for all GPIO interrupts. Actually setting
|
|
* the handler is needed only once, but doing it for every port
|
|
* is more robust and easier.
|
|
*/
|
|
irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
|
|
} else {
|
|
/* setup one handler for each entry */
|
|
irq_set_chained_handler_and_data(port->irq,
|
|
mx3_gpio_irq_handler, port);
|
|
if (port->irq_high > 0)
|
|
/* setup handler for GPIO 16 to 31 */
|
|
irq_set_chained_handler_and_data(port->irq_high,
|
|
mx3_gpio_irq_handler,
|
|
port);
|
|
}
|
|
|
|
err = bgpio_init(&port->gc, &pdev->dev, 4,
|
|
port->base + GPIO_PSR,
|
|
port->base + GPIO_DR, NULL,
|
|
port->base + GPIO_GDIR, NULL,
|
|
BGPIOF_READ_OUTPUT_REG_SET);
|
|
if (err)
|
|
goto out_bgio;
|
|
|
|
if (of_property_read_bool(np, "gpio-ranges")) {
|
|
port->gc.request = gpiochip_generic_request;
|
|
port->gc.free = gpiochip_generic_free;
|
|
}
|
|
|
|
port->gc.to_irq = mxc_gpio_to_irq;
|
|
port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
|
|
pdev->id * 32;
|
|
|
|
err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
|
|
if (err)
|
|
goto out_bgio;
|
|
|
|
irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
|
|
if (irq_base < 0) {
|
|
err = irq_base;
|
|
goto out_bgio;
|
|
}
|
|
|
|
port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
|
|
&irq_domain_simple_ops, NULL);
|
|
if (!port->domain) {
|
|
err = -ENODEV;
|
|
goto out_irqdesc_free;
|
|
}
|
|
|
|
/* gpio-mxc can be a generic irq chip */
|
|
err = mxc_gpio_init_gc(port, irq_base);
|
|
if (err < 0)
|
|
goto out_irqdomain_remove;
|
|
|
|
list_add_tail(&port->node, &mxc_gpio_ports);
|
|
|
|
return 0;
|
|
|
|
out_irqdomain_remove:
|
|
irq_domain_remove(port->domain);
|
|
out_irqdesc_free:
|
|
irq_free_descs(irq_base, 32);
|
|
out_bgio:
|
|
dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
|
|
return err;
|
|
}
|
|
|
|
static struct platform_driver mxc_gpio_driver = {
|
|
.driver = {
|
|
.name = "gpio-mxc",
|
|
.of_match_table = mxc_gpio_dt_ids,
|
|
},
|
|
.probe = mxc_gpio_probe,
|
|
.id_table = mxc_gpio_devtype,
|
|
};
|
|
|
|
static int __init gpio_mxc_init(void)
|
|
{
|
|
return platform_driver_register(&mxc_gpio_driver);
|
|
}
|
|
subsys_initcall(gpio_mxc_init);
|