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c23e7f01cf
SEGV_BNDERR was introduced initially for supporting the Intel MPX, but
fell into disuse after the MPX support was removed. The LoongArch
bounds-checking instructions behave very differently than MPX, but
overall the interface is still kind of suitable for conveying the
information to userland when bounds-checking assertions trigger, so we
wouldn't have to invent more UAPI. Specifically, when the BCE triggers,
a SEGV_BNDERR is sent to userland, with si_addr set to the out-of-bounds
address or value (in asrt{gt,le}'s case), and one of si_lower or
si_upper set to the configured bound depending on the faulting
instruction. The other bound is set to either 0 or ULONG_MAX to resemble
a range with both lower and upper bounds.
Note that it is possible to have si_addr == si_lower in case of a
failing asrtgt or {ld,st}gt, because those instructions test for strict
greater-than relationship. This should not pose a problem for userland,
though, because the faulting PC is available for the application to
associate back to the exact instruction for figuring out the
expectation.
Example exception context generated by a faulting `asrtgt.d t0, t1`
(assert t0 > t1 or BCE) with t0=100 and t1=200:
> pc 00005555558206a4 ra 00007ffff2d854fc tp 00007ffff2f2f180 sp 00007ffffbf9fb80
> a0 0000000000000002 a1 00007ffffbf9fce8 a2 00007ffffbf9fd00 a3 00007ffff2ed4558
> a4 0000000000000000 a5 00007ffff2f044c8 a6 00007ffffbf9fce0 a7 fffffffffffff000
> t0 0000000000000064 t1 00000000000000c8 t2 00007ffffbfa2d5e t3 00007ffff2f12aa0
> t4 00007ffff2ed6158 t5 00007ffff2ed6158 t6 000000000000002e t7 0000000003d8f538
> t8 0000000000000005 u0 0000000000000000 s9 0000000000000000 s0 00007ffffbf9fce8
> s1 0000000000000002 s2 0000000000000000 s3 00007ffff2f2c038 s4 0000555555820610
> s5 00007ffff2ed5000 s6 0000555555827e38 s7 00007ffffbf9fd00 s8 0000555555827e38
> ra: 00007ffff2d854fc
> ERA: 00005555558206a4
> CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE)
> PRMD: 00000007 (PPLV3 +PIE -PWE)
> EUEN: 00000000 (-FPE -SXE -ASXE -BTE)
> ECFG: 0007181c (LIE=2-4,11-12 VS=7)
> ESTAT: 000a0000 [BCE] (IS= ECode=10 EsubCode=0)
> PRID: 0014c010 (Loongson-64bit, Loongson-3A5000)
Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
99 lines
2.1 KiB
ArmAsm
99 lines
2.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2002, 2007 Maciej W. Rozycki
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* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/loongarch.h>
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#include <asm/regdef.h>
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#include <asm/fpregdef.h>
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#include <asm/stackframe.h>
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#include <asm/thread_info.h>
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.align 5
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SYM_FUNC_START(__arch_cpu_idle)
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/* start of rollback region */
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LONG_L t0, tp, TI_FLAGS
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nop
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andi t0, t0, _TIF_NEED_RESCHED
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bnez t0, 1f
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nop
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nop
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nop
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idle 0
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/* end of rollback region */
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1: jr ra
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SYM_FUNC_END(__arch_cpu_idle)
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SYM_FUNC_START(handle_vint)
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BACKUP_T0T1
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SAVE_ALL
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la_abs t1, __arch_cpu_idle
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LONG_L t0, sp, PT_ERA
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/* 32 byte rollback region */
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ori t0, t0, 0x1f
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xori t0, t0, 0x1f
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bne t0, t1, 1f
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LONG_S t0, sp, PT_ERA
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1: move a0, sp
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move a1, sp
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la_abs t0, do_vint
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jirl ra, t0, 0
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RESTORE_ALL_AND_RET
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SYM_FUNC_END(handle_vint)
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SYM_FUNC_START(except_vec_cex)
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b cache_parity_error
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SYM_FUNC_END(except_vec_cex)
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.macro build_prep_badv
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csrrd t0, LOONGARCH_CSR_BADV
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PTR_S t0, sp, PT_BVADDR
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.endm
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.macro build_prep_fcsr
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movfcsr2gr a1, fcsr0
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.endm
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.macro build_prep_none
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.endm
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.macro BUILD_HANDLER exception handler prep
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.align 5
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SYM_FUNC_START(handle_\exception)
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666:
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BACKUP_T0T1
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SAVE_ALL
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build_prep_\prep
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move a0, sp
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la_abs t0, do_\handler
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jirl ra, t0, 0
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668:
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RESTORE_ALL_AND_RET
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SYM_FUNC_END(handle_\exception)
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SYM_DATA(unwind_hint_\exception, .word 668b - 666b)
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.endm
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BUILD_HANDLER ade ade badv
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BUILD_HANDLER ale ale badv
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BUILD_HANDLER bce bce none
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BUILD_HANDLER bp bp none
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BUILD_HANDLER fpe fpe fcsr
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BUILD_HANDLER fpu fpu none
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BUILD_HANDLER lsx lsx none
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BUILD_HANDLER lasx lasx none
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BUILD_HANDLER lbt lbt none
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BUILD_HANDLER ri ri none
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BUILD_HANDLER watch watch none
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BUILD_HANDLER reserved reserved none /* others */
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SYM_FUNC_START(handle_sys)
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la_abs t0, handle_syscall
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jr t0
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SYM_FUNC_END(handle_sys)
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