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70fa895488
Before adding the directly controlled resets support it's reasonable to move the existing resets control functionality into a dedicated object for the sake of the CCU dividers clock driver simplification. After the new functionality was added clk-ccu-div.c would have got to a mixture of the weakly dependent clocks and resets methods. Splitting the methods up into the two objects will make the code easier to read and maintain. It shall also improve the code scalability (though hopefully we won't need this part that much in the future). The reset control functionality is now implemented in the framework of a single unit since splitting it up doesn't make much sense due to relatively simple reset operations. The ccu-rst.c has been designed to be looking like ccu-div.c or ccu-pll.c with two globally available methods for the sake of the code unification and better code readability. This commit doesn't provide any change in the CCU reset implementation semantics. As before the driver will support the trigger-like CCU resets only, which are responsible for the AXI-bus, APB-bus and SATA-ref blocks reset. The assert/de-assert-capable reset controls support will be added in the next commit. Note the CCU Clock dividers and resets functionality split up was possible due to not having any side-effects (at least we didn't found ones) of the regmap-based concurrent access of the common CCU dividers/reset CSRs. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220929225402.9696-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
52 lines
2.1 KiB
Text
52 lines
2.1 KiB
Text
# SPDX-License-Identifier: GPL-2.0-only
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config CLK_BAIKAL_T1
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bool "Baikal-T1 Clocks Control Unit interface"
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depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
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default MIPS_BAIKAL_T1
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help
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Clocks Control Unit is the core of Baikal-T1 SoC System Controller
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responsible for the chip subsystems clocking and resetting. It
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consists of multiple global clock domains, which can be reset by
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means of the CCU control registers. These domains and devices placed
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in them are fed with clocks generated by a hierarchy of PLLs,
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configurable and fixed clock dividers. Enable this option to be able
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to select Baikal-T1 CCU PLLs and Dividers drivers.
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if CLK_BAIKAL_T1
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config CLK_BT1_CCU_PLL
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bool "Baikal-T1 CCU PLLs support"
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select MFD_SYSCON
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default MIPS_BAIKAL_T1
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help
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Enable this to support the PLLs embedded into the Baikal-T1 SoC
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System Controller. These are five PLLs placed at the root of the
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clocks hierarchy, right after an external reference oscillator
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(normally of 25MHz). They are used to generate high frequency
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signals, which are either directly wired to the consumers (like
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CPUs, DDR, etc.) or passed over the clock dividers to be only
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then used as an individual reference clock of a target device.
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config CLK_BT1_CCU_DIV
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bool "Baikal-T1 CCU Dividers support"
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select MFD_SYSCON
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default MIPS_BAIKAL_T1
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help
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Enable this to support the CCU dividers used to distribute clocks
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between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
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SoC. CCU dividers can be either configurable or with fixed divider,
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either gateable or ungateable. Some of the CCU dividers can be as well
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used to reset the domains they're supplying clock to.
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config CLK_BT1_CCU_RST
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bool "Baikal-T1 CCU Resets support"
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select RESET_CONTROLLER
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select MFD_SYSCON
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default MIPS_BAIKAL_T1
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help
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Enable this to support the CCU reset blocks responsible for the
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AXI-bus and some subsystems reset. These are mainly the
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self-deasserted reset controls but there are several lines which
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can be directly asserted/de-asserted (PCIe and DDR sub-domains).
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endif
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