mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 05:44:11 +00:00
032bcf783e
- Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
92 lines
2.3 KiB
C
92 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Amlogic Meson-AXG Clock Controller Driver
|
|
*
|
|
* Copyright (c) 2016 BayLibre, SAS.
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
*
|
|
* Copyright (c) 2018 Amlogic, inc.
|
|
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
|
* Author: Yixun Lan <yixun.lan@amlogic.com>
|
|
*/
|
|
|
|
#include <linux/platform_device.h>
|
|
#include <linux/reset-controller.h>
|
|
#include <linux/mfd/syscon.h>
|
|
#include <linux/of.h>
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/slab.h>
|
|
#include "meson-aoclk.h"
|
|
|
|
static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
struct meson_aoclk_reset_controller *rstc =
|
|
container_of(rcdev, struct meson_aoclk_reset_controller, reset);
|
|
|
|
return regmap_write(rstc->regmap, rstc->data->reset_reg,
|
|
BIT(rstc->data->reset[id]));
|
|
}
|
|
|
|
static const struct reset_control_ops meson_aoclk_reset_ops = {
|
|
.reset = meson_aoclk_do_reset,
|
|
};
|
|
|
|
int meson_aoclkc_probe(struct platform_device *pdev)
|
|
{
|
|
struct meson_aoclk_reset_controller *rstc;
|
|
struct meson_aoclk_data *data;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np;
|
|
struct regmap *regmap;
|
|
int ret, clkid;
|
|
|
|
data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
|
|
if (!data)
|
|
return -ENODEV;
|
|
|
|
rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
|
|
if (!rstc)
|
|
return -ENOMEM;
|
|
|
|
np = of_get_parent(dev->of_node);
|
|
regmap = syscon_node_to_regmap(np);
|
|
of_node_put(np);
|
|
if (IS_ERR(regmap)) {
|
|
dev_err(dev, "failed to get regmap\n");
|
|
return PTR_ERR(regmap);
|
|
}
|
|
|
|
/* Reset Controller */
|
|
rstc->data = data;
|
|
rstc->regmap = regmap;
|
|
rstc->reset.ops = &meson_aoclk_reset_ops;
|
|
rstc->reset.nr_resets = data->num_reset;
|
|
rstc->reset.of_node = dev->of_node;
|
|
ret = devm_reset_controller_register(dev, &rstc->reset);
|
|
if (ret) {
|
|
dev_err(dev, "failed to register reset controller\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Populate regmap */
|
|
for (clkid = 0; clkid < data->num_clks; clkid++)
|
|
data->clks[clkid]->map = regmap;
|
|
|
|
/* Register all clks */
|
|
for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
|
|
if (!data->hw_clks.hws[clkid])
|
|
continue;
|
|
|
|
ret = devm_clk_hw_register(dev, data->hw_clks.hws[clkid]);
|
|
if (ret) {
|
|
dev_err(dev, "Clock registration failed\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
|
|
}
|
|
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
|
|
MODULE_LICENSE("GPL v2");
|