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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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032bcf783e
- Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#include "clk-regmap.h"
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#include "meson-eeclk.h"
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int meson_eeclkc_probe(struct platform_device *pdev)
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{
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const struct meson_eeclkc_data *data;
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struct device *dev = &pdev->dev;
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struct device_node *np;
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struct regmap *map;
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int ret, i;
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data = of_device_get_match_data(dev);
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if (!data)
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return -EINVAL;
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/* Get the hhi system controller node */
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np = of_get_parent(dev->of_node);
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map = syscon_node_to_regmap(np);
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of_node_put(np);
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if (IS_ERR(map)) {
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dev_err(dev,
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"failed to get HHI regmap\n");
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return PTR_ERR(map);
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}
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if (data->init_count)
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regmap_multi_reg_write(map, data->init_regs, data->init_count);
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/* Populate regmap for the regmap backed clocks */
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for (i = 0; i < data->regmap_clk_num; i++)
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data->regmap_clks[i]->map = map;
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for (i = 0; i < data->hw_clks.num; i++) {
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/* array might be sparse */
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if (!data->hw_clks.hws[i])
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continue;
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ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]);
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if (ret) {
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dev_err(dev, "Clock registration failed\n");
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return ret;
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}
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}
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return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
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}
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EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
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MODULE_LICENSE("GPL v2");
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