Stephen Boyd d10ebc7c64 Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next ... - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes		2023-08-30 14:37:45 -07:00
..
Kconfig	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-02-10 10:35:16 +01:00
Makefile	clk: renesas: Add RZ/V2M support using the rzg2l driver	2022-05-06 09:38:40 +02:00
clk-div6.c	clk: renesas: div6: Implement range checking	2021-05-11 09:58:13 +02:00
clk-div6.h	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
clk-emev2.c	clk: renesas: emev2: Remove obsolete clkdev registration	2023-07-27 14:32:41 +02:00
clk-mstp.c	clk: renesas: mstp: Convert to readl_poll_timeout_atomic()	2023-06-05 15:41:43 +02:00
clk-r8a73a4.c	clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg	2022-06-13 11:53:18 +02:00
clk-r8a7740.c	clk: renesas: r8a7740: Remove r8a7740_cpg.reg	2022-06-13 11:53:18 +02:00
clk-r8a7778.c	clk: renesas: r8a7778: Remove struct r8a7778_cpg	2022-06-13 11:53:18 +02:00
clk-r8a7779.c	clk: renesas: r8a7779: Remove struct r8a7779_cpg	2022-06-13 11:53:18 +02:00
clk-rz.c	clk: renesas: rza1: Remove struct rz_cpg	2022-06-13 11:53:18 +02:00
clk-sh73a0.c	clk: renesas: sh73a0: Remove sh73a0_cpg.reg	2022-06-13 11:53:18 +02:00
r7s9210-cpg-mssr.c	clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag	2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774b1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774c0-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774e1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a779a0-cpg-mssr.c	clk: renesas: r8a779a0: Add PWM clock	2023-05-08 09:14:33 +02:00
r8a779f0-cpg-mssr.c	clk: renesas: r8a779f0: Fix Ethernet Switch clocks	2022-11-16 09:05:59 +01:00
r8a779g0-cpg-mssr.c	clk: renesas: r8a779g0: Add VIN clocks	2023-03-06 10:42:14 +01:00
r8a7742-cpg-mssr.c	clk: renesas: r8a7742: Add clk entry for VSPR	2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a7796-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77470-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77970-cpg-mssr.c	clk: renesas: r8a77970: Add Z2 clock	2023-03-10 17:07:07 +01:00
r8a77980-cpg-mssr.c	clk: renesas: r8a77980: Add I2C5 clock	2023-03-30 16:44:04 +02:00
r8a77990-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77995-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r9a06g032-clocks.c	clk: renesas: r9a06g032: Add a determine_rate hook	2023-06-08 18:39:29 -07:00
r9a07g043-cpg.c	clk: renesas: r9a07g043: Add MTU3a clock and reset entry	2023-07-25 11:12:28 +02:00
r9a07g044-cpg.c	clk: renesas: r9a07g044: Add clock and reset entries for CRU	2023-01-12 17:18:48 +01:00
r9a09g011-cpg.c	clk: renesas: r9a09g011: Add CSI related clocks	2023-07-10 09:31:53 +02:00
rcar-cpg-lib.c	clk: renesas: rcar-gen3: Switch to new SD clock handling	2021-11-19 11:32:39 +01:00
rcar-cpg-lib.h	clk: renesas: rcar-gen3: Switch to new SD clock handling	2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c	clk: renesas: Zero init clk_init_data	2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h	clk: renesas: rcar-gen2: Change multipliers and dividers to u8	2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c	clk: renesas: rcar-gen3: Add support for ZG clock	2023-07-10 09:31:29 +02:00
rcar-gen3-cpg.h	clk: renesas: rcar-gen3: Add support for ZG clock	2023-07-10 09:31:29 +02:00
rcar-gen4-cpg.c	clk: renesas: r8a779g0: Add custom clock for PLL2	2023-01-24 10:11:50 +01:00
rcar-gen4-cpg.h	clk: renesas: r8a779g0: Add custom clock for PLL2	2023-01-24 10:11:50 +01:00
rcar-usb2-clock-sel.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
renesas-cpg-mssr.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
renesas-cpg-mssr.h	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-02-10 10:35:16 +01:00
rzg2l-cpg.c	Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next	2023-08-30 14:37:45 -07:00
rzg2l-cpg.h	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	2023-05-23 09:06:50 +02:00