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12382ad051
Ports S, T, U and V are in a separate controller that is part of the FSI
domain. Remove their definitions from the MAIN controller definitions to
get rid of the confusion.
This technically breaks ABI compatibility with old device trees. However
it doesn't cause issues in practice. The GPIO pins impacted by this are
used for non-critical functionality.
Fixes: a8b10f3d12 ("dt-bindings: gpio: Add Tegra234 support")
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
[treding@nvidia.com: rewrite commit message]
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */
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/*
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* This header provides constants for binding nvidia,tegra234-gpio*.
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*
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* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
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* provide names for this.
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*
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* The second cell contains standard flag values specified in gpio.h.
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*/
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#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
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#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
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#include <dt-bindings/gpio/gpio.h>
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/* GPIOs implemented by main GPIO controller */
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#define TEGRA234_MAIN_GPIO_PORT_A 0
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#define TEGRA234_MAIN_GPIO_PORT_B 1
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#define TEGRA234_MAIN_GPIO_PORT_C 2
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#define TEGRA234_MAIN_GPIO_PORT_D 3
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#define TEGRA234_MAIN_GPIO_PORT_E 4
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#define TEGRA234_MAIN_GPIO_PORT_F 5
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#define TEGRA234_MAIN_GPIO_PORT_G 6
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#define TEGRA234_MAIN_GPIO_PORT_H 7
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#define TEGRA234_MAIN_GPIO_PORT_I 8
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#define TEGRA234_MAIN_GPIO_PORT_J 9
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#define TEGRA234_MAIN_GPIO_PORT_K 10
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#define TEGRA234_MAIN_GPIO_PORT_L 11
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#define TEGRA234_MAIN_GPIO_PORT_M 12
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#define TEGRA234_MAIN_GPIO_PORT_N 13
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#define TEGRA234_MAIN_GPIO_PORT_P 14
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#define TEGRA234_MAIN_GPIO_PORT_Q 15
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#define TEGRA234_MAIN_GPIO_PORT_R 16
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#define TEGRA234_MAIN_GPIO_PORT_X 17
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#define TEGRA234_MAIN_GPIO_PORT_Y 18
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#define TEGRA234_MAIN_GPIO_PORT_Z 19
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#define TEGRA234_MAIN_GPIO_PORT_AC 20
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#define TEGRA234_MAIN_GPIO_PORT_AD 21
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#define TEGRA234_MAIN_GPIO_PORT_AE 22
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#define TEGRA234_MAIN_GPIO_PORT_AF 23
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#define TEGRA234_MAIN_GPIO_PORT_AG 24
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#define TEGRA234_MAIN_GPIO(port, offset) \
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((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)
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/* GPIOs implemented by AON GPIO controller */
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#define TEGRA234_AON_GPIO_PORT_AA 0
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#define TEGRA234_AON_GPIO_PORT_BB 1
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#define TEGRA234_AON_GPIO_PORT_CC 2
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#define TEGRA234_AON_GPIO_PORT_DD 3
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#define TEGRA234_AON_GPIO_PORT_EE 4
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#define TEGRA234_AON_GPIO_PORT_GG 5
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#define TEGRA234_AON_GPIO(port, offset) \
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((TEGRA234_AON_GPIO_PORT_##port * 8) + offset)
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#endif
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