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![Horatiu Vultur](/assets/img/avatar_default.png)
Add basic support for MRP. The HW will just trap all MRP frames on the ring ports to CPU and allow the SW to process them. In this way it is possible to for this node to behave both as MRM and MRC. Current limitations are: - it doesn't support Interconnect roles. - it supports only a single ring. - the HW should be able to do forwarding of MRP Test frames so the SW will not need to do this. So it would be able to have the role MRC without SW support. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
223 lines
9.9 KiB
C
223 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* Copyright 2019-2021 NXP Semiconductors
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*/
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#ifndef _NET_DSA_TAG_OCELOT_H
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#define _NET_DSA_TAG_OCELOT_H
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#include <linux/packing.h>
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#define OCELOT_TAG_LEN 16
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#define OCELOT_SHORT_PREFIX_LEN 4
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#define OCELOT_LONG_PREFIX_LEN 16
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#define OCELOT_TOTAL_TAG_LEN (OCELOT_SHORT_PREFIX_LEN + OCELOT_TAG_LEN)
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/* The CPU injection header and the CPU extraction header can have 3 types of
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* prefixes: long, short and no prefix. The format of the header itself is the
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* same in all 3 cases.
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*
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* Extraction with long prefix:
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*
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* +-------------------+-------------------+------+------+------------+-------+
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* | ff:ff:ff:ff:ff:ff | fe:ff:ff:ff:ff:ff | 8880 | 000a | extraction | frame |
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* | | | | | header | |
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* +-------------------+-------------------+------+------+------------+-------+
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* 48 bits 48 bits 16 bits 16 bits 128 bits
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*
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* Extraction with short prefix:
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*
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* +------+------+------------+-------+
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* | 8880 | 000a | extraction | frame |
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* | | | header | |
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* +------+------+------------+-------+
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* 16 bits 16 bits 128 bits
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*
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* Extraction with no prefix:
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*
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* +------------+-------+
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* | extraction | frame |
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* | header | |
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* +------------+-------+
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* 128 bits
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*
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*
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* Injection with long prefix:
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*
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* +-------------------+-------------------+------+------+------------+-------+
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* | any dmac | any smac | 8880 | 000a | injection | frame |
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* | | | | | header | |
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* +-------------------+-------------------+------+------+------------+-------+
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* 48 bits 48 bits 16 bits 16 bits 128 bits
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*
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* Injection with short prefix:
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*
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* +------+------+------------+-------+
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* | 8880 | 000a | injection | frame |
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* | | | header | |
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* +------+------+------------+-------+
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* 16 bits 16 bits 128 bits
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*
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* Injection with no prefix:
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*
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* +------------+-------+
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* | injection | frame |
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* | header | |
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* +------------+-------+
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* 128 bits
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*
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* The injection header looks like this (network byte order, bit 127
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* is part of lowest address byte in memory, bit 0 is part of highest
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* address byte):
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*
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* +------+------+------+------+------+------+------+------+
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* 127:120 |BYPASS| MASQ | MASQ_PORT |REW_OP|REW_OP|
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* +------+------+------+------+------+------+------+------+
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* 119:112 | REW_OP |
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* +------+------+------+------+------+------+------+------+
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* 111:104 | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 103: 96 | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 95: 88 | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 87: 80 | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 79: 72 | RSV |
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* +------+------+------+------+------+------+------+------+
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* 71: 64 | RSV | DEST |
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* +------+------+------+------+------+------+------+------+
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* 63: 56 | DEST |
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* +------+------+------+------+------+------+------+------+
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* 55: 48 | RSV |
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* +------+------+------+------+------+------+------+------+
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* 47: 40 | RSV | SRC_PORT | RSV |TFRM_TIMER|
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* +------+------+------+------+------+------+------+------+
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* 39: 32 | TFRM_TIMER | RSV |
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* +------+------+------+------+------+------+------+------+
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* 31: 24 | RSV | DP | POP_CNT | CPUQ |
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* +------+------+------+------+------+------+------+------+
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* 23: 16 | CPUQ | QOS_CLASS |TAG_TYPE|
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* +------+------+------+------+------+------+------+------+
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* 15: 8 | PCP | DEI | VID |
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* +------+------+------+------+------+------+------+------+
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* 7: 0 | VID |
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* +------+------+------+------+------+------+------+------+
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*
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* And the extraction header looks like this:
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*
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* +------+------+------+------+------+------+------+------+
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* 127:120 | RSV | REW_OP |
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* +------+------+------+------+------+------+------+------+
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* 119:112 | REW_OP | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 111:104 | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 103: 96 | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 95: 88 | REW_VAL |
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* +------+------+------+------+------+------+------+------+
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* 87: 80 | REW_VAL | LLEN |
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* +------+------+------+------+------+------+------+------+
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* 79: 72 | LLEN | WLEN |
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* +------+------+------+------+------+------+------+------+
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* 71: 64 | WLEN | RSV |
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* +------+------+------+------+------+------+------+------+
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* 63: 56 | RSV |
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* +------+------+------+------+------+------+------+------+
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* 55: 48 | RSV |
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* +------+------+------+------+------+------+------+------+
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* 47: 40 | RSV | SRC_PORT | ACL_ID |
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* +------+------+------+------+------+------+------+------+
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* 39: 32 | ACL_ID | RSV | SFLOW_ID |
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* +------+------+------+------+------+------+------+------+
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* 31: 24 |ACL_HIT| DP | LRN_FLAGS | CPUQ |
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* +------+------+------+------+------+------+------+------+
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* 23: 16 | CPUQ | QOS_CLASS |TAG_TYPE|
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* +------+------+------+------+------+------+------+------+
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* 15: 8 | PCP | DEI | VID |
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* +------+------+------+------+------+------+------+------+
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* 7: 0 | VID |
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* +------+------+------+------+------+------+------+------+
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*/
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static inline void ocelot_xfh_get_rew_val(void *extraction, u64 *rew_val)
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{
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packing(extraction, rew_val, 116, 85, OCELOT_TAG_LEN, UNPACK, 0);
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}
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static inline void ocelot_xfh_get_len(void *extraction, u64 *len)
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{
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u64 llen, wlen;
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packing(extraction, &llen, 84, 79, OCELOT_TAG_LEN, UNPACK, 0);
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packing(extraction, &wlen, 78, 71, OCELOT_TAG_LEN, UNPACK, 0);
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*len = 60 * wlen + llen - 80;
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}
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static inline void ocelot_xfh_get_src_port(void *extraction, u64 *src_port)
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{
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packing(extraction, src_port, 46, 43, OCELOT_TAG_LEN, UNPACK, 0);
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}
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static inline void ocelot_xfh_get_cpuq(void *extraction, u64 *cpuq)
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{
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packing(extraction, cpuq, 28, 20, OCELOT_TAG_LEN, UNPACK, 0);
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}
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static inline void ocelot_xfh_get_qos_class(void *extraction, u64 *qos_class)
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{
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packing(extraction, qos_class, 19, 17, OCELOT_TAG_LEN, UNPACK, 0);
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}
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static inline void ocelot_xfh_get_tag_type(void *extraction, u64 *tag_type)
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{
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packing(extraction, tag_type, 16, 16, OCELOT_TAG_LEN, UNPACK, 0);
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}
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static inline void ocelot_xfh_get_vlan_tci(void *extraction, u64 *vlan_tci)
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{
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packing(extraction, vlan_tci, 15, 0, OCELOT_TAG_LEN, UNPACK, 0);
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}
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static inline void ocelot_ifh_set_bypass(void *injection, u64 bypass)
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{
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packing(injection, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0);
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}
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static inline void ocelot_ifh_set_rew_op(void *injection, u64 rew_op)
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{
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packing(injection, &rew_op, 125, 117, OCELOT_TAG_LEN, PACK, 0);
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}
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static inline void ocelot_ifh_set_dest(void *injection, u64 dest)
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{
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packing(injection, &dest, 67, 56, OCELOT_TAG_LEN, PACK, 0);
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}
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static inline void ocelot_ifh_set_qos_class(void *injection, u64 qos_class)
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{
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packing(injection, &qos_class, 19, 17, OCELOT_TAG_LEN, PACK, 0);
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}
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static inline void seville_ifh_set_dest(void *injection, u64 dest)
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{
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packing(injection, &dest, 67, 57, OCELOT_TAG_LEN, PACK, 0);
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}
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static inline void ocelot_ifh_set_src(void *injection, u64 src)
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{
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packing(injection, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0);
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}
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static inline void ocelot_ifh_set_tag_type(void *injection, u64 tag_type)
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{
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packing(injection, &tag_type, 16, 16, OCELOT_TAG_LEN, PACK, 0);
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}
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static inline void ocelot_ifh_set_vid(void *injection, u64 vid)
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{
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packing(injection, &vid, 11, 0, OCELOT_TAG_LEN, PACK, 0);
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}
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#endif
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