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![Huy Nguyen](/assets/img/avatar_default.png)
Add new FTE in TX IPsec FT per IPsec state. It has the same matching criteria as the RX steering rule. The IPsec FT is created/destroyed when the first/last rule is added/deleted respectively. Signed-off-by: Huy Nguyen <huyn@mellanox.com> Reviewed-by: Boris Pismenny <borisp@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
550 lines
12 KiB
C
550 lines
12 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_QP_H
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#define MLX5_QP_H
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#include <linux/mlx5/device.h>
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#include <linux/mlx5/driver.h>
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#define MLX5_INVALID_LKEY 0x100
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/* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
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#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8)
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#define MLX5_DIF_SIZE 8
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#define MLX5_STRIDE_BLOCK_OP 0x400
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#define MLX5_CPY_GRD_MASK 0xc0
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#define MLX5_CPY_APP_MASK 0x30
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#define MLX5_CPY_REF_MASK 0x0f
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#define MLX5_BSF_INC_REFTAG (1 << 6)
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#define MLX5_BSF_INL_VALID (1 << 15)
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#define MLX5_BSF_REFRESH_DIF (1 << 14)
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#define MLX5_BSF_REPEAT_BLOCK (1 << 7)
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#define MLX5_BSF_APPTAG_ESCAPE 0x1
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#define MLX5_BSF_APPREF_ESCAPE 0x2
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enum mlx5_qp_optpar {
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MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
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MLX5_QP_OPTPAR_RRE = 1 << 1,
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MLX5_QP_OPTPAR_RAE = 1 << 2,
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MLX5_QP_OPTPAR_RWE = 1 << 3,
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MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
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MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
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MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
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MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
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MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
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MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
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MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
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MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
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MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
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MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
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MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15,
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MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
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MLX5_QP_OPTPAR_SRQN = 1 << 18,
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MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
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MLX5_QP_OPTPAR_DC_HS = 1 << 20,
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MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
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MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25,
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};
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enum mlx5_qp_state {
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MLX5_QP_STATE_RST = 0,
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MLX5_QP_STATE_INIT = 1,
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MLX5_QP_STATE_RTR = 2,
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MLX5_QP_STATE_RTS = 3,
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MLX5_QP_STATE_SQER = 4,
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MLX5_QP_STATE_SQD = 5,
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MLX5_QP_STATE_ERR = 6,
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MLX5_QP_STATE_SQ_DRAINING = 7,
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MLX5_QP_STATE_SUSPENDED = 9,
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MLX5_QP_NUM_STATE,
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MLX5_QP_STATE,
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MLX5_QP_STATE_BAD,
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};
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enum {
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MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
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MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
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MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
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MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
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};
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enum {
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MLX5_QP_ST_RC = 0x0,
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MLX5_QP_ST_UC = 0x1,
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MLX5_QP_ST_UD = 0x2,
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MLX5_QP_ST_XRC = 0x3,
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MLX5_QP_ST_MLX = 0x4,
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MLX5_QP_ST_DCI = 0x5,
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MLX5_QP_ST_DCT = 0x6,
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MLX5_QP_ST_QP0 = 0x7,
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MLX5_QP_ST_QP1 = 0x8,
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MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
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MLX5_QP_ST_RAW_IPV6 = 0xa,
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MLX5_QP_ST_SNIFFER = 0xb,
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MLX5_QP_ST_SYNC_UMR = 0xe,
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MLX5_QP_ST_PTP_1588 = 0xd,
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MLX5_QP_ST_REG_UMR = 0xc,
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MLX5_QP_ST_MAX
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};
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enum {
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MLX5_QP_PM_MIGRATED = 0x3,
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MLX5_QP_PM_ARMED = 0x0,
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MLX5_QP_PM_REARM = 0x1
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};
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enum {
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MLX5_NON_ZERO_RQ = 0x0,
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MLX5_SRQ_RQ = 0x1,
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MLX5_CRQ_RQ = 0x2,
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MLX5_ZERO_LEN_RQ = 0x3
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};
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/* TODO REM */
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enum {
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/* params1 */
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MLX5_QP_BIT_SRE = 1 << 15,
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MLX5_QP_BIT_SWE = 1 << 14,
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MLX5_QP_BIT_SAE = 1 << 13,
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/* params2 */
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MLX5_QP_BIT_RRE = 1 << 15,
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MLX5_QP_BIT_RWE = 1 << 14,
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MLX5_QP_BIT_RAE = 1 << 13,
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MLX5_QP_BIT_RIC = 1 << 4,
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MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
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MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
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MLX5_QP_BIT_CC_MASTER = 1 << 0
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};
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enum {
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MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
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MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
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MLX5_WQE_CTRL_SOLICITED = 1 << 1,
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};
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enum {
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MLX5_SEND_WQE_DS = 16,
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MLX5_SEND_WQE_BB = 64,
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};
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#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
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enum {
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MLX5_SEND_WQE_MAX_WQEBBS = 16,
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};
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enum {
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MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
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MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
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MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
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MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
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MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
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};
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enum {
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MLX5_FENCE_MODE_NONE = 0 << 5,
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MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
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MLX5_FENCE_MODE_FENCE = 2 << 5,
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MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
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MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
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};
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enum {
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MLX5_RCV_DBR = 0,
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MLX5_SND_DBR = 1,
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};
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enum {
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MLX5_FLAGS_INLINE = 1<<7,
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MLX5_FLAGS_CHECK_FREE = 1<<5,
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};
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struct mlx5_wqe_fmr_seg {
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__be32 flags;
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__be32 mem_key;
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__be64 buf_list;
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__be64 start_addr;
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__be64 reg_len;
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__be32 offset;
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__be32 page_size;
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u32 reserved[2];
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};
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struct mlx5_wqe_ctrl_seg {
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__be32 opmod_idx_opcode;
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__be32 qpn_ds;
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u8 signature;
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u8 rsvd[2];
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u8 fm_ce_se;
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union {
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__be32 general_id;
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__be32 imm;
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__be32 umr_mkey;
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__be32 tis_tir_num;
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};
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};
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#define MLX5_WQE_CTRL_DS_MASK 0x3f
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#define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
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#define MLX5_WQE_CTRL_QPN_SHIFT 8
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#define MLX5_WQE_DS_UNITS 16
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#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
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#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
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#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
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enum {
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MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
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MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
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MLX5_ETH_WQE_L3_CSUM = 1 << 6,
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MLX5_ETH_WQE_L4_CSUM = 1 << 7,
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};
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enum {
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MLX5_ETH_WQE_SVLAN = 1 << 0,
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MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
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MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
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MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
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MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
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MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30,
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MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
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};
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enum {
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MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0,
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MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1,
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MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4,
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MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5,
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};
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enum {
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MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
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};
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struct mlx5_wqe_eth_seg {
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u8 swp_outer_l4_offset;
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u8 swp_outer_l3_offset;
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u8 swp_inner_l4_offset;
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u8 swp_inner_l3_offset;
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u8 cs_flags;
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u8 swp_flags;
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__be16 mss;
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__be32 flow_table_metadata;
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union {
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struct {
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__be16 sz;
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u8 start[2];
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} inline_hdr;
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struct {
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__be16 type;
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__be16 vlan_tci;
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} insert;
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__be32 trailer;
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};
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};
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struct mlx5_wqe_xrc_seg {
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__be32 xrc_srqn;
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u8 rsvd[12];
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};
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struct mlx5_wqe_masked_atomic_seg {
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__be64 swap_add;
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__be64 compare;
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__be64 swap_add_mask;
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__be64 compare_mask;
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};
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struct mlx5_base_av {
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union {
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struct {
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__be32 qkey;
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__be32 reserved;
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} qkey;
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__be64 dc_key;
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} key;
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__be32 dqp_dct;
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u8 stat_rate_sl;
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u8 fl_mlid;
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union {
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__be16 rlid;
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__be16 udp_sport;
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};
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};
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struct mlx5_av {
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union {
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struct {
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__be32 qkey;
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__be32 reserved;
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} qkey;
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__be64 dc_key;
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} key;
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__be32 dqp_dct;
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u8 stat_rate_sl;
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u8 fl_mlid;
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union {
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__be16 rlid;
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__be16 udp_sport;
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};
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u8 reserved0[4];
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u8 rmac[6];
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u8 tclass;
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u8 hop_limit;
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__be32 grh_gid_fl;
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u8 rgid[16];
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};
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struct mlx5_ib_ah {
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struct ib_ah ibah;
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struct mlx5_av av;
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u8 xmit_port;
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};
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static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
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{
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return container_of(ibah, struct mlx5_ib_ah, ibah);
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}
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struct mlx5_wqe_datagram_seg {
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struct mlx5_av av;
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};
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struct mlx5_wqe_raddr_seg {
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__be64 raddr;
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__be32 rkey;
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u32 reserved;
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};
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struct mlx5_wqe_atomic_seg {
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__be64 swap_add;
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__be64 compare;
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};
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struct mlx5_wqe_data_seg {
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__be32 byte_count;
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__be32 lkey;
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__be64 addr;
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};
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struct mlx5_wqe_umr_ctrl_seg {
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u8 flags;
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u8 rsvd0[3];
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__be16 xlt_octowords;
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union {
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__be16 xlt_offset;
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__be16 bsf_octowords;
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};
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__be64 mkey_mask;
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__be32 xlt_offset_47_16;
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u8 rsvd1[28];
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};
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struct mlx5_seg_set_psv {
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__be32 psv_num;
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__be16 syndrome;
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__be16 status;
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__be32 transient_sig;
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__be32 ref_tag;
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};
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struct mlx5_seg_get_psv {
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u8 rsvd[19];
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u8 num_psv;
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__be32 l_key;
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__be64 va;
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__be32 psv_index[4];
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};
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struct mlx5_seg_check_psv {
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u8 rsvd0[2];
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__be16 err_coalescing_op;
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u8 rsvd1[2];
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__be16 xport_err_op;
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u8 rsvd2[2];
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__be16 xport_err_mask;
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u8 rsvd3[7];
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u8 num_psv;
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__be32 l_key;
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__be64 va;
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__be32 psv_index[4];
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};
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struct mlx5_rwqe_sig {
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u8 rsvd0[4];
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u8 signature;
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u8 rsvd1[11];
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};
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struct mlx5_wqe_signature_seg {
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u8 rsvd0[4];
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u8 signature;
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u8 rsvd1[11];
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};
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#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
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struct mlx5_wqe_inline_seg {
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__be32 byte_count;
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__be32 data[];
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};
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enum mlx5_sig_type {
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MLX5_DIF_CRC = 0x1,
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MLX5_DIF_IPCS = 0x2,
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};
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struct mlx5_bsf_inl {
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__be16 vld_refresh;
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__be16 dif_apptag;
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__be32 dif_reftag;
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u8 sig_type;
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u8 rp_inv_seed;
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u8 rsvd[3];
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u8 dif_inc_ref_guard_check;
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__be16 dif_app_bitmask_check;
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};
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struct mlx5_bsf {
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struct mlx5_bsf_basic {
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u8 bsf_size_sbs;
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u8 check_byte_mask;
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union {
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u8 copy_byte_mask;
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u8 bs_selector;
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u8 rsvd_wflags;
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} wire;
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union {
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u8 bs_selector;
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u8 rsvd_mflags;
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} mem;
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__be32 raw_data_size;
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__be32 w_bfs_psv;
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__be32 m_bfs_psv;
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} basic;
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struct mlx5_bsf_ext {
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__be32 t_init_gen_pro_size;
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__be32 rsvd_epi_size;
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__be32 w_tfs_psv;
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__be32 m_tfs_psv;
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} ext;
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struct mlx5_bsf_inl w_inl;
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struct mlx5_bsf_inl m_inl;
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};
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struct mlx5_mtt {
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__be64 ptag;
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};
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struct mlx5_klm {
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__be32 bcount;
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__be32 key;
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__be64 va;
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};
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struct mlx5_stride_block_entry {
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__be16 stride;
|
|
__be16 bcount;
|
|
__be32 key;
|
|
__be64 va;
|
|
};
|
|
|
|
struct mlx5_stride_block_ctrl_seg {
|
|
__be32 bcount_per_cycle;
|
|
__be32 op;
|
|
__be32 repeat_count;
|
|
u16 rsvd;
|
|
__be16 num_entries;
|
|
};
|
|
|
|
struct mlx5_core_qp {
|
|
struct mlx5_core_rsc_common common; /* must be first */
|
|
void (*event) (struct mlx5_core_qp *, int);
|
|
int qpn;
|
|
struct mlx5_rsc_debug *dbg;
|
|
int pid;
|
|
u16 uid;
|
|
};
|
|
|
|
struct mlx5_core_dct {
|
|
struct mlx5_core_qp mqp;
|
|
struct completion drained;
|
|
};
|
|
|
|
int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
|
|
void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
|
|
|
|
static inline const char *mlx5_qp_type_str(int type)
|
|
{
|
|
switch (type) {
|
|
case MLX5_QP_ST_RC: return "RC";
|
|
case MLX5_QP_ST_UC: return "C";
|
|
case MLX5_QP_ST_UD: return "UD";
|
|
case MLX5_QP_ST_XRC: return "XRC";
|
|
case MLX5_QP_ST_MLX: return "MLX";
|
|
case MLX5_QP_ST_QP0: return "QP0";
|
|
case MLX5_QP_ST_QP1: return "QP1";
|
|
case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
|
|
case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
|
|
case MLX5_QP_ST_SNIFFER: return "SNIFFER";
|
|
case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
|
|
case MLX5_QP_ST_PTP_1588: return "PTP_1588";
|
|
case MLX5_QP_ST_REG_UMR: return "REG_UMR";
|
|
default: return "Invalid transport type";
|
|
}
|
|
}
|
|
|
|
static inline const char *mlx5_qp_state_str(int state)
|
|
{
|
|
switch (state) {
|
|
case MLX5_QP_STATE_RST:
|
|
return "RST";
|
|
case MLX5_QP_STATE_INIT:
|
|
return "INIT";
|
|
case MLX5_QP_STATE_RTR:
|
|
return "RTR";
|
|
case MLX5_QP_STATE_RTS:
|
|
return "RTS";
|
|
case MLX5_QP_STATE_SQER:
|
|
return "SQER";
|
|
case MLX5_QP_STATE_SQD:
|
|
return "SQD";
|
|
case MLX5_QP_STATE_ERR:
|
|
return "ERR";
|
|
case MLX5_QP_STATE_SQ_DRAINING:
|
|
return "SQ_DRAINING";
|
|
case MLX5_QP_STATE_SUSPENDED:
|
|
return "SUSPENDED";
|
|
default: return "Invalid QP state";
|
|
}
|
|
}
|
|
|
|
#endif /* MLX5_QP_H */
|