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4c236d5dc8
This patch adds support to use new LMTST lines for NPA batch free and burst SQE flush. Adds new dev_hw_ops structure to hold platform specific functions and create new files cn10k.c and cn10k.h. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
37 lines
1.1 KiB
C
37 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __SOC_OTX2_ASM_H
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#define __SOC_OTX2_ASM_H
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#if defined(CONFIG_ARM64)
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/*
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* otx2_lmt_flush is used for LMT store operation.
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* On octeontx2 platform CPT instruction enqueue and
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* NIX packet send are only possible via LMTST
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* operations and it uses LDEOR instruction targeting
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* the coprocessor address.
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*/
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#define otx2_lmt_flush(ioaddr) \
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({ \
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u64 result = 0; \
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__asm__ volatile(".cpu generic+lse\n" \
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"ldeor xzr, %x[rf], [%[rs]]" \
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: [rf]"=r" (result) \
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: [rs]"r" (ioaddr)); \
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(result); \
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})
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#define cn10k_lmt_flush(val, addr) \
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({ \
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__asm__ volatile(".cpu generic+lse\n" \
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"steor %x[rf],[%[rs]]" \
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: [rf]"+r"(val) \
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: [rs]"r"(addr)); \
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})
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#else
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#define otx2_lmt_flush(ioaddr) ({ 0; })
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#define cn10k_lmt_flush(val, addr) ({ addr = val; })
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#endif
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#endif /* __SOC_OTX2_ASM_H */
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