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![Wayne Boyer](/assets/img/avatar_default.png)
The cherryview device shares many characteristics with the valleyview device. When support was added to the driver for cherryview, the corresponding device info structure included .is_valleyview = 1. This is not correct and leads to some confusion. This patch changes .is_valleyview to .is_cherryview in the cherryview device info structure and simplifies the IS_CHERRYVIEW macro. Then where appropriate, instances of IS_VALLEYVIEW are replaced with IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent. v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro. Also add followup patches to fix issues discovered during the first review. (Ville) v3: Fix some style issues and one gen check. Remove CRT related changes as CRT is not supported on CHV. (Imre, Ville) v4: Make a few more optimizations. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449692975-14803-1-git-send-email-wayne.boyer@intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
604 lines
16 KiB
C
604 lines
16 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Shobhit Kumar <shobhit.kumar@intel.com>
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* Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
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*/
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#include <linux/kernel.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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#include "intel_dsi.h"
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#define DSI_HSS_PACKET_SIZE 4
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#define DSI_HSE_PACKET_SIZE 4
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#define DSI_HSA_PACKET_EXTRA_SIZE 6
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#define DSI_HBP_PACKET_EXTRA_SIZE 6
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#define DSI_HACTIVE_PACKET_EXTRA_SIZE 6
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#define DSI_HFP_PACKET_EXTRA_SIZE 6
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#define DSI_EOTP_PACKET_SIZE 4
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static int dsi_pixel_format_bpp(int pixel_format)
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{
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int bpp;
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switch (pixel_format) {
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default:
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case VID_MODE_FORMAT_RGB888:
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case VID_MODE_FORMAT_RGB666_LOOSE:
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bpp = 24;
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break;
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case VID_MODE_FORMAT_RGB666:
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bpp = 18;
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break;
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case VID_MODE_FORMAT_RGB565:
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bpp = 16;
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break;
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}
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return bpp;
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}
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struct dsi_mnp {
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u32 dsi_pll_ctrl;
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u32 dsi_pll_div;
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};
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static const u32 lfsr_converts[] = {
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426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
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461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
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106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
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71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
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};
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#ifdef DSI_CLK_FROM_RR
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static u32 dsi_rr_formula(const struct drm_display_mode *mode,
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int pixel_format, int video_mode_format,
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int lane_count, bool eotp)
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{
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u32 bpp;
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u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp;
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u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes;
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u32 bytes_per_line, bytes_per_frame;
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u32 num_frames;
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u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes;
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u32 dsi_bit_clock_hz;
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u32 dsi_clk;
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bpp = dsi_pixel_format_bpp(pixel_format);
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hactive = mode->hdisplay;
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vactive = mode->vdisplay;
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hfp = mode->hsync_start - mode->hdisplay;
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hsync = mode->hsync_end - mode->hsync_start;
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hbp = mode->htotal - mode->hsync_end;
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vfp = mode->vsync_start - mode->vdisplay;
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vsync = mode->vsync_end - mode->vsync_start;
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vbp = mode->vtotal - mode->vsync_end;
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hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8);
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hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8);
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hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8);
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hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8);
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bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes +
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DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE +
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hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE +
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hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE +
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hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE;
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/*
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* XXX: Need to accurately calculate LP to HS transition timeout and add
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* it to bytes_per_line/bytes_per_frame.
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*/
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if (eotp && video_mode_format == VIDEO_MODE_BURST)
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bytes_per_line += DSI_EOTP_PACKET_SIZE;
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bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line +
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vactive * bytes_per_line + vfp * bytes_per_line;
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if (eotp &&
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(video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ||
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video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS))
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bytes_per_frame += DSI_EOTP_PACKET_SIZE;
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num_frames = drm_mode_vrefresh(mode);
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bytes_per_x_frames = num_frames * bytes_per_frame;
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bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;
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/* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */
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dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8;
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dsi_clk = dsi_bit_clock_hz / 1000;
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if (eotp && video_mode_format == VIDEO_MODE_BURST)
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dsi_clk *= 2;
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return dsi_clk;
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}
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#else
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/* Get DSI clock from pixel clock */
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static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
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{
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u32 dsi_clk_khz;
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u32 bpp = dsi_pixel_format_bpp(pixel_format);
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/* DSI data rate = pixel clock * bits per pixel / lane count
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pixel clock is converted from KHz to Hz */
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dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
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return dsi_clk_khz;
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}
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#endif
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static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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struct dsi_mnp *dsi_mnp, int target_dsi_clk)
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{
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unsigned int calc_m = 0, calc_p = 0;
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unsigned int m_min, m_max, p_min = 2, p_max = 6;
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unsigned int m, n, p;
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int ref_clk;
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int delta = target_dsi_clk;
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u32 m_seed;
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/* target_dsi_clk is expected in kHz */
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if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
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DRM_ERROR("DSI CLK Out of Range\n");
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return -ECHRNG;
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}
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if (IS_CHERRYVIEW(dev_priv)) {
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ref_clk = 100000;
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n = 4;
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m_min = 70;
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m_max = 96;
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} else {
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ref_clk = 25000;
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n = 1;
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m_min = 62;
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m_max = 92;
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}
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for (m = m_min; m <= m_max && delta; m++) {
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for (p = p_min; p <= p_max && delta; p++) {
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/*
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* Find the optimal m and p divisors with minimal delta
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* +/- the required clock
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*/
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int calc_dsi_clk = (m * ref_clk) / (p * n);
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int d = abs(target_dsi_clk - calc_dsi_clk);
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if (d < delta) {
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delta = d;
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calc_m = m;
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calc_p = p;
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}
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}
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}
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/* register has log2(N1), this works fine for powers of two */
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n = ffs(n) - 1;
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m_seed = lfsr_converts[calc_m - 62];
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dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
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dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT |
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m_seed << DSI_PLL_M1_DIV_SHIFT;
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return 0;
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}
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/*
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* XXX: The muxing and gating is hard coded for now. Need to add support for
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* sharing PLLs with two DSI outputs.
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*/
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static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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int ret;
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struct dsi_mnp dsi_mnp;
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u32 dsi_clk;
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dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
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intel_dsi->lane_count);
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ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
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if (ret) {
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DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
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return;
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}
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if (intel_dsi->ports & (1 << PORT_A))
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dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
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if (intel_dsi->ports & (1 << PORT_C))
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dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
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DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
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dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
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}
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static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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u32 tmp;
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DRM_DEBUG_KMS("\n");
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mutex_lock(&dev_priv->sb_lock);
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vlv_configure_dsi_pll(encoder);
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/* wait at least 0.5 us after ungating before enabling VCO */
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usleep_range(1, 10);
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tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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tmp |= DSI_PLL_VCO_EN;
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
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if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
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DSI_PLL_LOCK, 20)) {
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mutex_unlock(&dev_priv->sb_lock);
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DRM_ERROR("DSI PLL lock failed\n");
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return;
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}
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mutex_unlock(&dev_priv->sb_lock);
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DRM_DEBUG_KMS("DSI PLL locked\n");
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}
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static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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u32 tmp;
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DRM_DEBUG_KMS("\n");
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mutex_lock(&dev_priv->sb_lock);
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tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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tmp &= ~DSI_PLL_VCO_EN;
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tmp |= DSI_PLL_LDO_GATE;
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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u32 val;
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DRM_DEBUG_KMS("\n");
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val = I915_READ(BXT_DSI_PLL_ENABLE);
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val &= ~BXT_DSI_PLL_DO_ENABLE;
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I915_WRITE(BXT_DSI_PLL_ENABLE, val);
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/*
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* PLL lock should deassert within 200us.
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* Wait up to 1ms before timing out.
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*/
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if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
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& BXT_DSI_PLL_LOCKED) == 0, 1))
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DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
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}
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static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
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{
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int bpp = dsi_pixel_format_bpp(pixel_format);
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WARN(bpp != pipe_bpp,
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"bpp match assertion failure (expected %d, current %d)\n",
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bpp, pipe_bpp);
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}
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u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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u32 dsi_clock, pclk;
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u32 pll_ctl, pll_div;
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u32 m = 0, p = 0, n;
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int refclk = 25000;
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int i;
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DRM_DEBUG_KMS("\n");
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mutex_lock(&dev_priv->sb_lock);
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pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
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mutex_unlock(&dev_priv->sb_lock);
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/* mask out other bits and extract the P1 divisor */
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pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
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pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
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/* N1 divisor */
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n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
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n = 1 << n; /* register has log2(N1) */
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/* mask out the other bits and extract the M1 divisor */
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pll_div &= DSI_PLL_M1_DIV_MASK;
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pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
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while (pll_ctl) {
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pll_ctl = pll_ctl >> 1;
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p++;
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}
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p--;
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if (!p) {
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DRM_ERROR("wrong P1 divisor\n");
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
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if (lfsr_converts[i] == pll_div)
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break;
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}
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if (i == ARRAY_SIZE(lfsr_converts)) {
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DRM_ERROR("wrong m_seed programmed\n");
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return 0;
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}
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m = i + 62;
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dsi_clock = (m * refclk) / (p * n);
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/* pixel_format and pipe_bpp should agree */
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assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
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pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
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return pclk;
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}
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u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
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{
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u32 pclk;
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u32 dsi_clk;
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u32 dsi_ratio;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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/* Divide by zero */
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if (!pipe_bpp) {
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DRM_ERROR("Invalid BPP(0)\n");
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return 0;
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}
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dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
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BXT_DSI_PLL_RATIO_MASK;
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/* Invalid DSI ratio ? */
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if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
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dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
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DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
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return 0;
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}
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dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
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/* pixel_format and pipe_bpp should agree */
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assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
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pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
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DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
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return pclk;
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}
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static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
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{
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u32 temp;
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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temp = I915_READ(MIPI_CTRL(port));
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temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
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I915_WRITE(MIPI_CTRL(port), temp |
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intel_dsi->escape_clk_div <<
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ESCAPE_CLOCK_DIVIDER_SHIFT);
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}
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/* Program BXT Mipi clocks and dividers */
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static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
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{
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u32 tmp;
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u32 divider;
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u32 dsi_rate;
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u32 pll_ratio;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
/* Clear old configurations */
|
|
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
|
|
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
|
|
tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
|
|
tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
|
|
tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
|
|
|
|
/* Get the current DSI rate(actual) */
|
|
pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
|
|
BXT_DSI_PLL_RATIO_MASK;
|
|
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
|
|
|
|
/* Max possible output of clock is 39.5 MHz, program value -1 */
|
|
divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
|
|
tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
|
|
|
|
/*
|
|
* Tx escape clock must be as close to 20MHz possible, but should
|
|
* not exceed it. Hence select divide by 2
|
|
*/
|
|
tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
|
|
|
|
tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
|
|
|
|
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
|
|
}
|
|
|
|
static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
|
u8 dsi_ratio;
|
|
u32 dsi_clk;
|
|
u32 val;
|
|
|
|
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
|
|
intel_dsi->lane_count);
|
|
|
|
/*
|
|
* From clock diagram, to get PLL ratio divider, divide double of DSI
|
|
* link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
|
|
* round 'up' the result
|
|
*/
|
|
dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
|
|
if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
|
|
dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
|
|
DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
|
|
* Spec says both have to be programmed, even if one is not getting
|
|
* used. Configure MIPI_CLOCK_CTL dividers in modeset
|
|
*/
|
|
val = I915_READ(BXT_DSI_PLL_CTL);
|
|
val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
|
|
val &= ~BXT_DSI_FREQ_SEL_MASK;
|
|
val &= ~BXT_DSI_PLL_RATIO_MASK;
|
|
val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
|
|
|
|
/* As per recommendation from hardware team,
|
|
* Prog PVD ratio =1 if dsi ratio <= 50
|
|
*/
|
|
if (dsi_ratio <= 50) {
|
|
val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
|
|
val |= BXT_DSI_PLL_PVD_RATIO_1;
|
|
}
|
|
|
|
I915_WRITE(BXT_DSI_PLL_CTL, val);
|
|
POSTING_READ(BXT_DSI_PLL_CTL);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
|
enum port port;
|
|
u32 val;
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
val = I915_READ(BXT_DSI_PLL_ENABLE);
|
|
|
|
if (val & BXT_DSI_PLL_DO_ENABLE) {
|
|
WARN(1, "DSI PLL already enabled. Disabling it.\n");
|
|
val &= ~BXT_DSI_PLL_DO_ENABLE;
|
|
I915_WRITE(BXT_DSI_PLL_ENABLE, val);
|
|
}
|
|
|
|
/* Configure PLL vales */
|
|
if (!bxt_configure_dsi_pll(encoder)) {
|
|
DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
|
|
return;
|
|
}
|
|
|
|
/* Program TX, RX, Dphy clocks */
|
|
for_each_dsi_port(port, intel_dsi->ports)
|
|
bxt_dsi_program_clocks(encoder->base.dev, port);
|
|
|
|
/* Enable DSI PLL */
|
|
val = I915_READ(BXT_DSI_PLL_ENABLE);
|
|
val |= BXT_DSI_PLL_DO_ENABLE;
|
|
I915_WRITE(BXT_DSI_PLL_ENABLE, val);
|
|
|
|
/* Timeout and fail if PLL not locked */
|
|
if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
|
|
DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
|
|
return;
|
|
}
|
|
|
|
DRM_DEBUG_KMS("DSI PLL locked\n");
|
|
}
|
|
|
|
void intel_enable_dsi_pll(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
|
vlv_enable_dsi_pll(encoder);
|
|
else if (IS_BROXTON(dev))
|
|
bxt_enable_dsi_pll(encoder);
|
|
}
|
|
|
|
void intel_disable_dsi_pll(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
|
vlv_disable_dsi_pll(encoder);
|
|
else if (IS_BROXTON(dev))
|
|
bxt_disable_dsi_pll(encoder);
|
|
}
|
|
|
|
static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
|
|
{
|
|
u32 tmp;
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
/* Clear old configurations */
|
|
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
|
|
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
|
|
tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
|
|
tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
|
|
tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
|
|
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
|
|
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
|
|
}
|
|
|
|
void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
if (IS_BROXTON(dev))
|
|
bxt_dsi_reset_clocks(encoder, port);
|
|
else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
|
vlv_dsi_reset_clocks(encoder, port);
|
|
}
|