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![Daniel Vetter](/assets/img/avatar_default.png)
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Merge tag 'v4.4-rc2' into drm-intel-next-queued
Linux 4.4-rc2
Backmerge to get at
commit 1b0e3a049e
Author: Imre Deak <imre.deak@intel.com>
Date: Thu Nov 5 23:04:11 2015 +0200
drm/i915/skl: disable display side power well support for now
so that we can proplery re-eanble skl power wells in -next.
Conflicts are just adjacent lines changed, except for intel_fbdev.c
where we need to interleave the changs. Nothing nefarious.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
637 lines
19 KiB
C
637 lines
19 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Vinit Azad <vinit.azad@intel.com>
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* Ben Widawsky <ben@bwidawsk.net>
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* Dave Gordon <david.s.gordon@intel.com>
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* Alex Dai <yu.dai@intel.com>
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*/
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#include <linux/firmware.h>
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#include "i915_drv.h"
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#include "intel_guc.h"
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/**
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* DOC: GuC-specific firmware loader
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*
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* intel_guc:
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* Top level structure of guc. It handles firmware loading and manages client
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* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
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* ExecList submission.
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*
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* Firmware versioning:
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* The firmware build process will generate a version header file with major and
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* minor version defined. The versions are built into CSS header of firmware.
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* i915 kernel driver set the minimal firmware version required per platform.
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* The firmware installation package will install (symbolic link) proper version
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* of firmware.
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*
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* GuC address space:
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* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
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* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
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* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
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* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
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*
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* Firmware log:
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* Firmware log is enabled by setting i915.guc_log_level to non-negative level.
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* Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
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* i915_guc_load_status will print out firmware loading status and scratch
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* registers value.
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*
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*/
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#define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
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MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
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/* User-friendly representation of an enum */
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const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
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{
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switch (status) {
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case GUC_FIRMWARE_FAIL:
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return "FAIL";
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case GUC_FIRMWARE_NONE:
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return "NONE";
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case GUC_FIRMWARE_PENDING:
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return "PENDING";
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case GUC_FIRMWARE_SUCCESS:
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return "SUCCESS";
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default:
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return "UNKNOWN!";
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}
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};
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static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *ring;
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int i, irqs;
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/* tell all command streamers NOT to forward interrupts and vblank to GuC */
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irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
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irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
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for_each_ring(ring, dev_priv, i)
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I915_WRITE(RING_MODE_GEN7(ring), irqs);
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/* route all GT interrupts to the host */
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I915_WRITE(GUC_BCS_RCS_IER, 0);
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I915_WRITE(GUC_VCS2_VCS1_IER, 0);
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I915_WRITE(GUC_WD_VECS_IER, 0);
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}
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static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *ring;
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int i, irqs;
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/* tell all command streamers to forward interrupts and vblank to GuC */
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irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
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irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
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for_each_ring(ring, dev_priv, i)
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I915_WRITE(RING_MODE_GEN7(ring), irqs);
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/* route USER_INTERRUPT to Host, all others are sent to GuC. */
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irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
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GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
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/* These three registers have the same bit definitions */
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I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
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I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
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I915_WRITE(GUC_WD_VECS_IER, ~irqs);
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}
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static u32 get_gttype(struct drm_i915_private *dev_priv)
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{
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/* XXX: GT type based on PCI device ID? field seems unused by fw */
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return 0;
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}
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static u32 get_core_family(struct drm_i915_private *dev_priv)
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{
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switch (INTEL_INFO(dev_priv)->gen) {
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case 9:
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return GFXCORE_FAMILY_GEN9;
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default:
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DRM_ERROR("GUC: unsupported core family\n");
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return GFXCORE_FAMILY_UNKNOWN;
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}
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}
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static void set_guc_init_params(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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u32 params[GUC_CTL_MAX_DWORDS];
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int i;
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memset(¶ms, 0, sizeof(params));
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params[GUC_CTL_DEVICE_INFO] |=
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(get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
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(get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
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/*
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* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
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* second. This ARAR is calculated by:
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* Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
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*/
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params[GUC_CTL_ARAT_HIGH] = 0;
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params[GUC_CTL_ARAT_LOW] = 100000000;
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params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
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params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
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GUC_CTL_VCS2_ENABLED;
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if (i915.guc_log_level >= 0) {
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params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
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params[GUC_CTL_DEBUG] =
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i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
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}
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/* If GuC submission is enabled, set up additional parameters here */
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if (i915.enable_guc_submission) {
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u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
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u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
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pgs >>= PAGE_SHIFT;
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params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
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(ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
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params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
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/* Unmask this bit to enable the GuC's internal scheduler */
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params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
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}
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I915_WRITE(SOFT_SCRATCH(0), 0);
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for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
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I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
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}
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/*
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* Read the GuC status register (GUC_STATUS) and store it in the
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* specified location; then return a boolean indicating whether
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* the value matches either of two values representing completion
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* of the GuC boot process.
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*
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* This is used for polling the GuC status in a wait_for_atomic()
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* loop below.
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*/
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static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
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u32 *status)
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{
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u32 val = I915_READ(GUC_STATUS);
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u32 uk_val = val & GS_UKERNEL_MASK;
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*status = val;
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return (uk_val == GS_UKERNEL_READY ||
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((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
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}
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/*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Architecturally, the DMA engine is bidirectional, and can potentially even
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* transfer between GTT locations. This functionality is left out of the API
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* for now as there is no need for it.
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*
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* Note that GuC needs the CSS header plus uKernel code to be copied by the
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* DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
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*/
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static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
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{
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struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
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struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
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unsigned long offset;
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struct sg_table *sg = fw_obj->pages;
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u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
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int i, ret = 0;
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/* where RSA signature starts */
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offset = guc_fw->rsa_offset;
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/* Copy RSA signature from the fw image to HW for verification */
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sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
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for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
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I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
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/* The header plus uCode will be copied to WOPCM via DMA, excluding any
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* other components */
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I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
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/* Set the source address for the new blob */
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offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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/*
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* Set the DMA destination. Current uCode expects the code to be
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* loaded at 8k; locations below this are used for the stack.
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*/
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I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
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I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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/* Finally start the DMA */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
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/*
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* Spin-wait for the DMA to complete & the GuC to start up.
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* NB: Docs recommend not using the interrupt for completion.
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* Measurements indicate this should take no more than 20ms, so a
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* timeout here indicates that the GuC has failed and is unusable.
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* (Higher levels of the driver will attempt to fall back to
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* execlist mode if this happens.)
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*/
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ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
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DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
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I915_READ(DMA_CTRL), status);
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if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
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DRM_ERROR("GuC firmware signature verification failed\n");
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ret = -ENOEXEC;
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}
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DRM_DEBUG_DRIVER("returning %d\n", ret);
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return ret;
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}
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/*
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* Load the GuC firmware blob into the MinuteIA.
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*/
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static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
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{
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struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
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struct drm_device *dev = dev_priv->dev;
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int ret;
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ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
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if (ret) {
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DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
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return ret;
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}
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ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
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if (ret) {
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DRM_DEBUG_DRIVER("pin failed %d\n", ret);
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return ret;
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}
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/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
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I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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/* init WOPCM */
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I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
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I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
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/* Enable MIA caching. GuC clock gating is disabled. */
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I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
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/* WaDisableMinuteIaClockGating:skl,bxt */
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if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
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IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
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I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
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~GUC_ENABLE_MIA_CLOCK_GATING));
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}
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/* WaC6DisallowByGfxPause*/
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I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
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if (IS_BROXTON(dev))
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I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
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else
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I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
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if (IS_GEN9(dev)) {
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/* DOP Clock Gating Enable for GuC clocks */
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I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
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I915_READ(GEN7_MISCCPCTL)));
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/* allows for 5us before GT can go to RC6 */
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I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
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}
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set_guc_init_params(dev_priv);
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ret = guc_ucode_xfer_dma(dev_priv);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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/*
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* We keep the object pages for reuse during resume. But we can unpin it
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* now that DMA has completed, so it doesn't continue to take up space.
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*/
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i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
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return ret;
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}
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/**
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* intel_guc_ucode_load() - load GuC uCode into the device
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* @dev: drm device
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*
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* Called from gem_init_hw() during driver loading and also after a GPU reset.
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*
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* The firmware image should have already been fetched into memory by the
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* earlier call to intel_guc_ucode_init(), so here we need only check that
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* is succeeded, and then transfer the image to the h/w.
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*
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* Return: non-zero code on error
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*/
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int intel_guc_ucode_load(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
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int err = 0;
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if (!i915.enable_guc_submission)
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return 0;
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DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
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intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
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intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
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direct_interrupts_to_host(dev_priv);
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if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
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return 0;
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if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
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guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
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return -ENOEXEC;
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guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
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DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
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intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
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switch (guc_fw->guc_fw_fetch_status) {
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case GUC_FIRMWARE_FAIL:
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/* something went wrong :( */
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err = -EIO;
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goto fail;
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case GUC_FIRMWARE_NONE:
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case GUC_FIRMWARE_PENDING:
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default:
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/* "can't happen" */
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WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
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guc_fw->guc_fw_path,
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intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
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guc_fw->guc_fw_fetch_status);
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err = -ENXIO;
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goto fail;
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case GUC_FIRMWARE_SUCCESS:
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break;
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}
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err = i915_guc_submission_init(dev);
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if (err)
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goto fail;
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err = guc_ucode_xfer(dev_priv);
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if (err)
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goto fail;
|
|
|
|
guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
|
|
|
|
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
|
|
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
|
|
intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
|
|
|
|
if (i915.enable_guc_submission) {
|
|
/* The execbuf_client will be recreated. Release it first. */
|
|
i915_guc_submission_disable(dev);
|
|
|
|
err = i915_guc_submission_enable(dev);
|
|
if (err)
|
|
goto fail;
|
|
direct_interrupts_to_guc(dev_priv);
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
|
|
guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
|
|
|
|
direct_interrupts_to_host(dev_priv);
|
|
i915_guc_submission_disable(dev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
|
|
{
|
|
struct drm_i915_gem_object *obj;
|
|
const struct firmware *fw;
|
|
struct guc_css_header *css;
|
|
size_t size;
|
|
int err;
|
|
|
|
DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
|
|
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
|
|
|
|
err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
|
|
if (err)
|
|
goto fail;
|
|
if (!fw)
|
|
goto fail;
|
|
|
|
DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
|
|
guc_fw->guc_fw_path, fw);
|
|
|
|
/* Check the size of the blob before examining buffer contents */
|
|
if (fw->size < sizeof(struct guc_css_header)) {
|
|
DRM_ERROR("Firmware header is missing\n");
|
|
goto fail;
|
|
}
|
|
|
|
css = (struct guc_css_header *)fw->data;
|
|
|
|
/* Firmware bits always start from header */
|
|
guc_fw->header_offset = 0;
|
|
guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
|
|
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
|
|
|
|
if (guc_fw->header_size != sizeof(struct guc_css_header)) {
|
|
DRM_ERROR("CSS header definition mismatch\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* then, uCode */
|
|
guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
|
|
guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
|
|
|
|
/* now RSA */
|
|
if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
|
|
DRM_ERROR("RSA key size is bad\n");
|
|
goto fail;
|
|
}
|
|
guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
|
|
guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
|
|
|
|
/* At least, it should have header, uCode and RSA. Size of all three. */
|
|
size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
|
|
if (fw->size < size) {
|
|
DRM_ERROR("Missing firmware components\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Header and uCode will be loaded to WOPCM. Size of the two. */
|
|
size = guc_fw->header_size + guc_fw->ucode_size;
|
|
|
|
/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
|
|
if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) {
|
|
DRM_ERROR("Firmware is too large to fit in WOPCM\n");
|
|
goto fail;
|
|
}
|
|
|
|
/*
|
|
* The GuC firmware image has the version number embedded at a well-known
|
|
* offset within the firmware blob; note that major / minor version are
|
|
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
|
|
* in terms of bytes (u8).
|
|
*/
|
|
guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
|
|
guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
|
|
|
|
if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
|
|
guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
|
|
DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
|
|
guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
|
|
guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
|
|
err = -ENOEXEC;
|
|
goto fail;
|
|
}
|
|
|
|
DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
|
|
guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
|
|
guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
if (IS_ERR_OR_NULL(obj)) {
|
|
err = obj ? PTR_ERR(obj) : -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
guc_fw->guc_fw_obj = obj;
|
|
guc_fw->guc_fw_size = fw->size;
|
|
|
|
DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
|
|
guc_fw->guc_fw_obj);
|
|
|
|
release_firmware(fw);
|
|
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
|
|
return;
|
|
|
|
fail:
|
|
DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
|
|
err, fw, guc_fw->guc_fw_obj);
|
|
DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
|
|
guc_fw->guc_fw_path, err);
|
|
|
|
obj = guc_fw->guc_fw_obj;
|
|
if (obj)
|
|
drm_gem_object_unreference(&obj->base);
|
|
guc_fw->guc_fw_obj = NULL;
|
|
|
|
release_firmware(fw); /* OK even if fw is NULL */
|
|
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
|
|
}
|
|
|
|
/**
|
|
* intel_guc_ucode_init() - define parameters and fetch firmware
|
|
* @dev: drm device
|
|
*
|
|
* Called early during driver load, but after GEM is initialised.
|
|
*
|
|
* The firmware will be transferred to the GuC's memory later,
|
|
* when intel_guc_ucode_load() is called.
|
|
*/
|
|
void intel_guc_ucode_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
|
const char *fw_path;
|
|
|
|
if (!HAS_GUC_SCHED(dev))
|
|
i915.enable_guc_submission = false;
|
|
|
|
if (!HAS_GUC_UCODE(dev)) {
|
|
fw_path = NULL;
|
|
} else if (IS_SKYLAKE(dev)) {
|
|
fw_path = I915_SKL_GUC_UCODE;
|
|
guc_fw->guc_fw_major_wanted = 4;
|
|
guc_fw->guc_fw_minor_wanted = 3;
|
|
} else {
|
|
i915.enable_guc_submission = false;
|
|
fw_path = ""; /* unknown device */
|
|
}
|
|
|
|
if (!i915.enable_guc_submission)
|
|
return;
|
|
|
|
guc_fw->guc_dev = dev;
|
|
guc_fw->guc_fw_path = fw_path;
|
|
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
|
|
guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
|
|
|
|
if (fw_path == NULL)
|
|
return;
|
|
|
|
if (*fw_path == '\0') {
|
|
DRM_ERROR("No GuC firmware known for this platform\n");
|
|
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
|
|
return;
|
|
}
|
|
|
|
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
|
|
DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
|
|
guc_fw_fetch(dev, guc_fw);
|
|
/* status must now be FAIL or SUCCESS */
|
|
}
|
|
|
|
/**
|
|
* intel_guc_ucode_fini() - clean up all allocated resources
|
|
* @dev: drm device
|
|
*/
|
|
void intel_guc_ucode_fini(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
|
|
|
direct_interrupts_to_host(dev_priv);
|
|
i915_guc_submission_fini(dev);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
if (guc_fw->guc_fw_obj)
|
|
drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
|
|
guc_fw->guc_fw_obj = NULL;
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
|
|
}
|