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![Linus Torvalds](/assets/img/avatar_default.png)
core: - Fix a few inconsistencies between UP and SMP vs. interrupt affinities - Small updates and cleanups all over the place drivers: - New driver for the LoongArch interrupt controller - New driver for the Renesas RZ/G2L interrupt controller - Hotpath optimization for SiFive PLIC - Workaround for broken PLIC edge triggered interrupts - Simall cleanups and improvements as usual -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmLn5agTHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoV2HD/4u0+09Fd8Awt1Knnb4CInmwFihZ/bu EiS1Air+MEJ/fyFb5sT/Dn8YdUWYA6a3ifpLMGBwrKCcb5pMwPEtI8uqjSmtgsN/ 2Z4o3N5v6EgM25CtrHNBrXK0E9Rz5Py49gm5p3K7+h4g63z9JwrM4G0Bvr8+krLS EV9IZU6kVmGC6gnG/MspkArsLk1rCM0PU0SJ2lEPsWd1fjhVSDfunvy/qnnzXRzz wjrcAf+a2Kgb1TMnpL6tx9d2Xx8KrKfODZTdOmPHrdv58F0EbJzapJnAVkYZDPtR LE2kQc2Qhdawx0kgNNNhvu9P6oZtpnK9N7KAhDQdw17sgrRygINjAMSEe2RykYL1 lK+lJOIzfyd2JkEuC/8w1ZezL88S0EaTNawrkxjJ8L3fa7WDbwilCC+1w95QydCv sQB137OaLKgWetcRsht9PLWFb4ujkWzxoPf2cPPsm81EzCicNtBuNPLReBTcNrWJ X2VPpbaqRK8t8bnkXRqhahbq7f8c86feoICHfA4c7T4eZUp/Oq6T8aNvf6WPgjae I2/FO6kxZj3CQqFkhJGhiZRtGZdx6HLCsL84A+2Ktsra+D8+/qecZCnkHYtz0Vo6 aFuGg+Wj+zuc2QfdaWwG8Dh5dijbxgHGHhzbh9znsWzytN9gfoBxuvBejf65i6sC In63mEkv35ttfA== =OnhF -----END PGP SIGNATURE----- Merge tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "Updates for interrupt core and drivers: Core: - Fix a few inconsistencies between UP and SMP vs interrupt affinities - Small updates and cleanups all over the place New drivers: - LoongArch interrupt controller - Renesas RZ/G2L interrupt controller Updates: - Hotpath optimization for SiFive PLIC - Workaround for broken PLIC edge triggered interrupts - Simall cleanups and improvements as usual" * tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits) irqchip/mmp: Declare init functions in common header file irqchip/mips-gic: Check the return value of ioremap() in gic_of_init() genirq: Use for_each_action_of_desc in actions_show() irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch irqchip: Add LoongArch CPU interrupt controller support irqchip: Add Loongson Extended I/O interrupt controller support irqchip/loongson-liointc: Add ACPI init support irqchip/loongson-pch-msi: Add ACPI init support irqchip/loongson-pch-pic: Add ACPI init support irqchip: Add Loongson PCH LPC controller support LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain LoongArch: Use ACPI_GENERIC_GSI for gsi handling genirq/generic_chip: Export irq_unmap_generic_chip ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback APCI: irq: Add support for multiple GSI domains LoongArch: Provisionally add ACPICA data structures irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains irqdomain: Report irq number for NOMAP domains irqchip/gic-v3: Fix comment typo dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC ...
825 lines
26 KiB
C
825 lines
26 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_GPIO_DRIVER_H
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#define __LINUX_GPIO_DRIVER_H
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#include <linux/device.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/lockdep.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/property.h>
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#include <linux/types.h>
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#include <asm/msi.h>
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struct gpio_desc;
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struct of_phandle_args;
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struct device_node;
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struct seq_file;
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struct gpio_device;
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struct module;
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enum gpiod_flags;
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enum gpio_lookup_flags;
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struct gpio_chip;
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union gpio_irq_fwspec {
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struct irq_fwspec fwspec;
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#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
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msi_alloc_info_t msiinfo;
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#endif
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};
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#define GPIO_LINE_DIRECTION_IN 1
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#define GPIO_LINE_DIRECTION_OUT 0
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/**
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* struct gpio_irq_chip - GPIO interrupt controller
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*/
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struct gpio_irq_chip {
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/**
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* @chip:
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*
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* GPIO IRQ chip implementation, provided by GPIO driver.
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*/
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struct irq_chip *chip;
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/**
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* @domain:
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*
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* Interrupt translation domain; responsible for mapping between GPIO
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* hwirq number and Linux IRQ number.
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*/
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struct irq_domain *domain;
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/**
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* @domain_ops:
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*
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* Table of interrupt domain operations for this IRQ chip.
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*/
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const struct irq_domain_ops *domain_ops;
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#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
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/**
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* @fwnode:
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*
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* Firmware node corresponding to this gpiochip/irqchip, necessary
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* for hierarchical irqdomain support.
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*/
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struct fwnode_handle *fwnode;
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/**
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* @parent_domain:
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*
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* If non-NULL, will be set as the parent of this GPIO interrupt
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* controller's IRQ domain to establish a hierarchical interrupt
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* domain. The presence of this will activate the hierarchical
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* interrupt support.
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*/
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struct irq_domain *parent_domain;
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/**
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* @child_to_parent_hwirq:
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*
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* This callback translates a child hardware IRQ offset to a parent
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* hardware IRQ offset on a hierarchical interrupt chip. The child
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* hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
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* ngpio field of struct gpio_chip) and the corresponding parent
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* hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
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* the driver. The driver can calculate this from an offset or using
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* a lookup table or whatever method is best for this chip. Return
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* 0 on successful translation in the driver.
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*
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* If some ranges of hardware IRQs do not have a corresponding parent
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* HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
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* @need_valid_mask to make these GPIO lines unavailable for
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* translation.
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*/
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int (*child_to_parent_hwirq)(struct gpio_chip *gc,
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unsigned int child_hwirq,
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unsigned int child_type,
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unsigned int *parent_hwirq,
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unsigned int *parent_type);
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/**
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* @populate_parent_alloc_arg :
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*
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* This optional callback allocates and populates the specific struct
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* for the parent's IRQ domain. If this is not specified, then
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* &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
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* variant named &gpiochip_populate_parent_fwspec_fourcell is also
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* available.
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*/
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int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
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union gpio_irq_fwspec *fwspec,
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unsigned int parent_hwirq,
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unsigned int parent_type);
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/**
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* @child_offset_to_irq:
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*
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* This optional callback is used to translate the child's GPIO line
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* offset on the GPIO chip to an IRQ number for the GPIO to_irq()
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* callback. If this is not specified, then a default callback will be
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* provided that returns the line offset.
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*/
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unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
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unsigned int pin);
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/**
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* @child_irq_domain_ops:
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*
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* The IRQ domain operations that will be used for this GPIO IRQ
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* chip. If no operations are provided, then default callbacks will
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* be populated to setup the IRQ hierarchy. Some drivers need to
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* supply their own translate function.
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*/
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struct irq_domain_ops child_irq_domain_ops;
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#endif
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/**
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* @handler:
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*
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* The IRQ handler to use (often a predefined IRQ core function) for
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* GPIO IRQs, provided by GPIO driver.
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*/
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irq_flow_handler_t handler;
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/**
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* @default_type:
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*
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* Default IRQ triggering type applied during GPIO driver
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* initialization, provided by GPIO driver.
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*/
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unsigned int default_type;
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/**
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* @lock_key:
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*
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* Per GPIO IRQ chip lockdep class for IRQ lock.
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*/
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struct lock_class_key *lock_key;
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/**
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* @request_key:
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*
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* Per GPIO IRQ chip lockdep class for IRQ request.
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*/
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struct lock_class_key *request_key;
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/**
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* @parent_handler:
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*
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* The interrupt handler for the GPIO chip's parent interrupts, may be
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* NULL if the parent interrupts are nested rather than cascaded.
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*/
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irq_flow_handler_t parent_handler;
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union {
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/**
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* @parent_handler_data:
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*
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* If @per_parent_data is false, @parent_handler_data is a
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* single pointer used as the data associated with every
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* parent interrupt.
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*/
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void *parent_handler_data;
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/**
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* @parent_handler_data_array:
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*
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* If @per_parent_data is true, @parent_handler_data_array is
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* an array of @num_parents pointers, and is used to associate
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* different data for each parent. This cannot be NULL if
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* @per_parent_data is true.
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*/
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void **parent_handler_data_array;
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};
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/**
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* @num_parents:
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*
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* The number of interrupt parents of a GPIO chip.
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*/
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unsigned int num_parents;
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/**
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* @parents:
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*
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* A list of interrupt parents of a GPIO chip. This is owned by the
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* driver, so the core will only reference this list, not modify it.
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*/
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unsigned int *parents;
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/**
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* @map:
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*
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* A list of interrupt parents for each line of a GPIO chip.
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*/
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unsigned int *map;
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/**
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* @threaded:
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*
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* True if set the interrupt handling uses nested threads.
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*/
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bool threaded;
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/**
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* @per_parent_data:
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*
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* True if parent_handler_data_array describes a @num_parents
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* sized array to be used as parent data.
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*/
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bool per_parent_data;
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/**
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* @initialized:
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*
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* Flag to track GPIO chip irq member's initialization.
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* This flag will make sure GPIO chip irq members are not used
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* before they are initialized.
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*/
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bool initialized;
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/**
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* @init_hw: optional routine to initialize hardware before
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* an IRQ chip will be added. This is quite useful when
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* a particular driver wants to clear IRQ related registers
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* in order to avoid undesired events.
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*/
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int (*init_hw)(struct gpio_chip *gc);
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/**
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* @init_valid_mask: optional routine to initialize @valid_mask, to be
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* used if not all GPIO lines are valid interrupts. Sometimes some
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* lines just cannot fire interrupts, and this routine, when defined,
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* is passed a bitmap in "valid_mask" and it will have ngpios
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* bits from 0..(ngpios-1) set to "1" as in valid. The callback can
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* then directly set some bits to "0" if they cannot be used for
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* interrupts.
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*/
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void (*init_valid_mask)(struct gpio_chip *gc,
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unsigned long *valid_mask,
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unsigned int ngpios);
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/**
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* @valid_mask:
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*
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* If not %NULL, holds bitmask of GPIOs which are valid to be included
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* in IRQ domain of the chip.
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*/
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unsigned long *valid_mask;
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/**
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* @first:
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*
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* Required for static IRQ allocation. If set, irq_domain_add_simple()
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* will allocate and map all IRQs during initialization.
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*/
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unsigned int first;
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/**
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* @irq_enable:
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*
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* Store old irq_chip irq_enable callback
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*/
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void (*irq_enable)(struct irq_data *data);
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/**
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* @irq_disable:
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*
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* Store old irq_chip irq_disable callback
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*/
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void (*irq_disable)(struct irq_data *data);
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/**
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* @irq_unmask:
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*
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* Store old irq_chip irq_unmask callback
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*/
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void (*irq_unmask)(struct irq_data *data);
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/**
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* @irq_mask:
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*
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* Store old irq_chip irq_mask callback
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*/
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void (*irq_mask)(struct irq_data *data);
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};
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/**
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* struct gpio_chip - abstract a GPIO controller
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* @label: a functional name for the GPIO device, such as a part
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* number or the name of the SoC IP-block implementing it.
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* @gpiodev: the internal state holder, opaque struct
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* @parent: optional parent device providing the GPIOs
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* @fwnode: optional fwnode providing this controller's properties
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* @owner: helps prevent removal of modules exporting active GPIOs
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* @request: optional hook for chip-specific activation, such as
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* enabling module power and clock; may sleep
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* @free: optional hook for chip-specific deactivation, such as
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* disabling module power and clock; may sleep
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* @get_direction: returns direction for signal "offset", 0=out, 1=in,
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* (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
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* or negative error. It is recommended to always implement this
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* function, even on input-only or output-only gpio chips.
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* @direction_input: configures signal "offset" as input, or returns error
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* This can be omitted on input-only or output-only gpio chips.
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* @direction_output: configures signal "offset" as output, or returns error
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* This can be omitted on input-only or output-only gpio chips.
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* @get: returns value for signal "offset", 0=low, 1=high, or negative error
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* @get_multiple: reads values for multiple signals defined by "mask" and
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* stores them in "bits", returns 0 on success or negative error
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* @set: assigns output value for signal "offset"
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* @set_multiple: assigns output values for multiple signals defined by "mask"
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* @set_config: optional hook for all kinds of settings. Uses the same
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* packed config format as generic pinconf.
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* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
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* implementation may not sleep
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* @dbg_show: optional routine to show contents in debugfs; default code
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* will be used when this is omitted, but custom code can show extra
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* state (such as pullup/pulldown configuration).
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* @init_valid_mask: optional routine to initialize @valid_mask, to be used if
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* not all GPIOs are valid.
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* @add_pin_ranges: optional routine to initialize pin ranges, to be used when
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* requires special mapping of the pins that provides GPIO functionality.
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* It is called after adding GPIO chip and before adding IRQ chip.
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* @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
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* enable hardware timestamp.
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* @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
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* disable hardware timestamp.
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* @base: identifies the first GPIO number handled by this chip;
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* or, if negative during registration, requests dynamic ID allocation.
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* DEPRECATION: providing anything non-negative and nailing the base
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* offset of GPIO chips is deprecated. Please pass -1 as base to
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* let gpiolib select the chip base in all possible cases. We want to
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* get rid of the static GPIO number space in the long run.
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* @ngpio: the number of GPIOs handled by this controller; the last GPIO
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* handled is (base + ngpio - 1).
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* @offset: when multiple gpio chips belong to the same device this
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* can be used as offset within the device so friendly names can
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* be properly assigned.
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* @names: if set, must be an array of strings to use as alternative
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* names for the GPIOs in this chip. Any entry in the array
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* may be NULL if there is no alias for the GPIO, however the
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* array must be @ngpio entries long. A name can include a single printk
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* format specifier for an unsigned int. It is substituted by the actual
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* number of the gpio.
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* @can_sleep: flag must be set iff get()/set() methods sleep, as they
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* must while accessing GPIO expander chips over I2C or SPI. This
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* implies that if the chip supports IRQs, these IRQs need to be threaded
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* as the chip access may sleep when e.g. reading out the IRQ status
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* registers.
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* @read_reg: reader function for generic GPIO
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* @write_reg: writer function for generic GPIO
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* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
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* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
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* generic GPIO core. It is for internal housekeeping only.
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* @reg_dat: data (in) register for generic GPIO
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* @reg_set: output set register (out=high) for generic GPIO
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* @reg_clr: output clear register (out=low) for generic GPIO
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* @reg_dir_out: direction out setting register for generic GPIO
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* @reg_dir_in: direction in setting register for generic GPIO
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* @bgpio_dir_unreadable: indicates that the direction register(s) cannot
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* be read and we need to rely on out internal state tracking.
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* @bgpio_bits: number of register bits used for a generic GPIO i.e.
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* <register width> * 8
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* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
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* shadowed and real data registers writes together.
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* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
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* safely.
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* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
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* direction safely. A "1" in this word means the line is set as
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* output.
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*
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* A gpio_chip can help platforms abstract various sources of GPIOs so
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* they can all be accessed through a common programming interface.
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* Example sources would be SOC controllers, FPGAs, multifunction
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* chips, dedicated GPIO expanders, and so on.
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*
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* Each chip controls a number of signals, identified in method calls
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* by "offset" values in the range 0..(@ngpio - 1). When those signals
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* are referenced through calls like gpio_get_value(gpio), the offset
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* is calculated by subtracting @base from the gpio number.
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*/
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struct gpio_chip {
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const char *label;
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struct gpio_device *gpiodev;
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struct device *parent;
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struct fwnode_handle *fwnode;
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struct module *owner;
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int (*request)(struct gpio_chip *gc,
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unsigned int offset);
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void (*free)(struct gpio_chip *gc,
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unsigned int offset);
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int (*get_direction)(struct gpio_chip *gc,
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unsigned int offset);
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int (*direction_input)(struct gpio_chip *gc,
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unsigned int offset);
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int (*direction_output)(struct gpio_chip *gc,
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unsigned int offset, int value);
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int (*get)(struct gpio_chip *gc,
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unsigned int offset);
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int (*get_multiple)(struct gpio_chip *gc,
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unsigned long *mask,
|
|
unsigned long *bits);
|
|
void (*set)(struct gpio_chip *gc,
|
|
unsigned int offset, int value);
|
|
void (*set_multiple)(struct gpio_chip *gc,
|
|
unsigned long *mask,
|
|
unsigned long *bits);
|
|
int (*set_config)(struct gpio_chip *gc,
|
|
unsigned int offset,
|
|
unsigned long config);
|
|
int (*to_irq)(struct gpio_chip *gc,
|
|
unsigned int offset);
|
|
|
|
void (*dbg_show)(struct seq_file *s,
|
|
struct gpio_chip *gc);
|
|
|
|
int (*init_valid_mask)(struct gpio_chip *gc,
|
|
unsigned long *valid_mask,
|
|
unsigned int ngpios);
|
|
|
|
int (*add_pin_ranges)(struct gpio_chip *gc);
|
|
|
|
int (*en_hw_timestamp)(struct gpio_chip *gc,
|
|
u32 offset,
|
|
unsigned long flags);
|
|
int (*dis_hw_timestamp)(struct gpio_chip *gc,
|
|
u32 offset,
|
|
unsigned long flags);
|
|
int base;
|
|
u16 ngpio;
|
|
u16 offset;
|
|
const char *const *names;
|
|
bool can_sleep;
|
|
|
|
#if IS_ENABLED(CONFIG_GPIO_GENERIC)
|
|
unsigned long (*read_reg)(void __iomem *reg);
|
|
void (*write_reg)(void __iomem *reg, unsigned long data);
|
|
bool be_bits;
|
|
void __iomem *reg_dat;
|
|
void __iomem *reg_set;
|
|
void __iomem *reg_clr;
|
|
void __iomem *reg_dir_out;
|
|
void __iomem *reg_dir_in;
|
|
bool bgpio_dir_unreadable;
|
|
int bgpio_bits;
|
|
raw_spinlock_t bgpio_lock;
|
|
unsigned long bgpio_data;
|
|
unsigned long bgpio_dir;
|
|
#endif /* CONFIG_GPIO_GENERIC */
|
|
|
|
#ifdef CONFIG_GPIOLIB_IRQCHIP
|
|
/*
|
|
* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
|
|
* to handle IRQs for most practical cases.
|
|
*/
|
|
|
|
/**
|
|
* @irq:
|
|
*
|
|
* Integrates interrupt chip functionality with the GPIO chip. Can be
|
|
* used to handle IRQs for most practical cases.
|
|
*/
|
|
struct gpio_irq_chip irq;
|
|
#endif /* CONFIG_GPIOLIB_IRQCHIP */
|
|
|
|
/**
|
|
* @valid_mask:
|
|
*
|
|
* If not %NULL, holds bitmask of GPIOs which are valid to be used
|
|
* from the chip.
|
|
*/
|
|
unsigned long *valid_mask;
|
|
|
|
#if defined(CONFIG_OF_GPIO)
|
|
/*
|
|
* If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
|
|
* the device tree automatically may have an OF translation
|
|
*/
|
|
|
|
/**
|
|
* @of_node:
|
|
*
|
|
* Pointer to a device tree node representing this GPIO controller.
|
|
*/
|
|
struct device_node *of_node;
|
|
|
|
/**
|
|
* @of_gpio_n_cells:
|
|
*
|
|
* Number of cells used to form the GPIO specifier.
|
|
*/
|
|
unsigned int of_gpio_n_cells;
|
|
|
|
/**
|
|
* @of_xlate:
|
|
*
|
|
* Callback to translate a device tree GPIO specifier into a chip-
|
|
* relative GPIO number and flags.
|
|
*/
|
|
int (*of_xlate)(struct gpio_chip *gc,
|
|
const struct of_phandle_args *gpiospec, u32 *flags);
|
|
|
|
/**
|
|
* @of_gpio_ranges_fallback:
|
|
*
|
|
* Optional hook for the case that no gpio-ranges property is defined
|
|
* within the device tree node "np" (usually DT before introduction
|
|
* of gpio-ranges). So this callback is helpful to provide the
|
|
* necessary backward compatibility for the pin ranges.
|
|
*/
|
|
int (*of_gpio_ranges_fallback)(struct gpio_chip *gc,
|
|
struct device_node *np);
|
|
|
|
#endif /* CONFIG_OF_GPIO */
|
|
};
|
|
|
|
extern const char *gpiochip_is_requested(struct gpio_chip *gc,
|
|
unsigned int offset);
|
|
|
|
/**
|
|
* for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
|
|
* @chip: the chip to query
|
|
* @i: loop variable
|
|
* @base: first GPIO in the range
|
|
* @size: amount of GPIOs to check starting from @base
|
|
* @label: label of current GPIO
|
|
*/
|
|
#define for_each_requested_gpio_in_range(chip, i, base, size, label) \
|
|
for (i = 0; i < size; i++) \
|
|
if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
|
|
|
|
/* Iterates over all requested GPIO of the given @chip */
|
|
#define for_each_requested_gpio(chip, i, label) \
|
|
for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
|
|
|
|
/* add/remove chips */
|
|
extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
|
struct lock_class_key *lock_key,
|
|
struct lock_class_key *request_key);
|
|
|
|
/**
|
|
* gpiochip_add_data() - register a gpio_chip
|
|
* @gc: the chip to register, with gc->base initialized
|
|
* @data: driver-private data associated with this chip
|
|
*
|
|
* Context: potentially before irqs will work
|
|
*
|
|
* When gpiochip_add_data() is called very early during boot, so that GPIOs
|
|
* can be freely used, the gc->parent device must be registered before
|
|
* the gpio framework's arch_initcall(). Otherwise sysfs initialization
|
|
* for GPIOs will fail rudely.
|
|
*
|
|
* gpiochip_add_data() must only be called after gpiolib initialization,
|
|
* i.e. after core_initcall().
|
|
*
|
|
* If gc->base is negative, this requests dynamic assignment of
|
|
* a range of valid GPIOs.
|
|
*
|
|
* Returns:
|
|
* A negative errno if the chip can't be registered, such as because the
|
|
* gc->base is invalid or already associated with a different chip.
|
|
* Otherwise it returns zero as a success code.
|
|
*/
|
|
#ifdef CONFIG_LOCKDEP
|
|
#define gpiochip_add_data(gc, data) ({ \
|
|
static struct lock_class_key lock_key; \
|
|
static struct lock_class_key request_key; \
|
|
gpiochip_add_data_with_key(gc, data, &lock_key, \
|
|
&request_key); \
|
|
})
|
|
#define devm_gpiochip_add_data(dev, gc, data) ({ \
|
|
static struct lock_class_key lock_key; \
|
|
static struct lock_class_key request_key; \
|
|
devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
|
|
&request_key); \
|
|
})
|
|
#else
|
|
#define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
|
|
#define devm_gpiochip_add_data(dev, gc, data) \
|
|
devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
|
|
#endif /* CONFIG_LOCKDEP */
|
|
|
|
static inline int gpiochip_add(struct gpio_chip *gc)
|
|
{
|
|
return gpiochip_add_data(gc, NULL);
|
|
}
|
|
extern void gpiochip_remove(struct gpio_chip *gc);
|
|
extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
|
|
struct lock_class_key *lock_key,
|
|
struct lock_class_key *request_key);
|
|
|
|
extern struct gpio_chip *gpiochip_find(void *data,
|
|
int (*match)(struct gpio_chip *gc, void *data));
|
|
|
|
bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
|
|
int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
|
|
void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
|
|
void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
|
|
void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
/* irq_data versions of the above */
|
|
int gpiochip_irq_reqres(struct irq_data *data);
|
|
void gpiochip_irq_relres(struct irq_data *data);
|
|
|
|
/* Paste this in your irq_chip structure */
|
|
#define GPIOCHIP_IRQ_RESOURCE_HELPERS \
|
|
.irq_request_resources = gpiochip_irq_reqres, \
|
|
.irq_release_resources = gpiochip_irq_relres
|
|
|
|
static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
|
|
const struct irq_chip *chip)
|
|
{
|
|
/* Yes, dropping const is ugly, but it isn't like we have a choice */
|
|
girq->chip = (struct irq_chip *)chip;
|
|
}
|
|
|
|
/* Line status inquiry for drivers */
|
|
bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
|
|
bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
/* Sleep persistence inquiry for drivers */
|
|
bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
|
|
bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
|
|
|
|
/* get driver data */
|
|
void *gpiochip_get_data(struct gpio_chip *gc);
|
|
|
|
struct bgpio_pdata {
|
|
const char *label;
|
|
int base;
|
|
int ngpio;
|
|
};
|
|
|
|
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
|
|
|
|
int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
|
|
union gpio_irq_fwspec *gfwspec,
|
|
unsigned int parent_hwirq,
|
|
unsigned int parent_type);
|
|
int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
|
|
union gpio_irq_fwspec *gfwspec,
|
|
unsigned int parent_hwirq,
|
|
unsigned int parent_type);
|
|
|
|
#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
|
|
|
|
int bgpio_init(struct gpio_chip *gc, struct device *dev,
|
|
unsigned long sz, void __iomem *dat, void __iomem *set,
|
|
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
|
|
unsigned long flags);
|
|
|
|
#define BGPIOF_BIG_ENDIAN BIT(0)
|
|
#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
|
|
#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
|
|
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
|
|
#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
|
|
#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
|
|
#define BGPIOF_NO_SET_ON_INPUT BIT(6)
|
|
|
|
int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hwirq);
|
|
void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
|
|
|
|
int gpiochip_irq_domain_activate(struct irq_domain *domain,
|
|
struct irq_data *data, bool reserve);
|
|
void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
|
|
struct irq_data *data);
|
|
|
|
bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
|
|
unsigned int offset);
|
|
|
|
#ifdef CONFIG_GPIOLIB_IRQCHIP
|
|
int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
|
|
struct irq_domain *domain);
|
|
#else
|
|
static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
|
|
struct irq_domain *domain)
|
|
{
|
|
WARN_ON(1);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
|
|
void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
|
|
int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
|
|
unsigned long config);
|
|
|
|
/**
|
|
* struct gpio_pin_range - pin range controlled by a gpio chip
|
|
* @node: list for maintaining set of pin ranges, used internally
|
|
* @pctldev: pinctrl device which handles corresponding pins
|
|
* @range: actual range of pins controlled by a gpio controller
|
|
*/
|
|
struct gpio_pin_range {
|
|
struct list_head node;
|
|
struct pinctrl_dev *pctldev;
|
|
struct pinctrl_gpio_range range;
|
|
};
|
|
|
|
#ifdef CONFIG_PINCTRL
|
|
|
|
int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
unsigned int npins);
|
|
int gpiochip_add_pingroup_range(struct gpio_chip *gc,
|
|
struct pinctrl_dev *pctldev,
|
|
unsigned int gpio_offset, const char *pin_group);
|
|
void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
|
|
|
|
#else /* ! CONFIG_PINCTRL */
|
|
|
|
static inline int
|
|
gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
unsigned int npins)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int
|
|
gpiochip_add_pingroup_range(struct gpio_chip *gc,
|
|
struct pinctrl_dev *pctldev,
|
|
unsigned int gpio_offset, const char *pin_group)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void
|
|
gpiochip_remove_pin_ranges(struct gpio_chip *gc)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_PINCTRL */
|
|
|
|
struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
|
|
unsigned int hwnum,
|
|
const char *label,
|
|
enum gpio_lookup_flags lflags,
|
|
enum gpiod_flags dflags);
|
|
void gpiochip_free_own_desc(struct gpio_desc *desc);
|
|
|
|
#ifdef CONFIG_GPIOLIB
|
|
|
|
/* lock/unlock as IRQ */
|
|
int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
|
|
void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
|
|
struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
|
|
|
|
#else /* CONFIG_GPIOLIB */
|
|
|
|
static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
|
|
{
|
|
/* GPIO can never have been requested */
|
|
WARN_ON(1);
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
|
|
unsigned int offset)
|
|
{
|
|
WARN_ON(1);
|
|
return -EINVAL;
|
|
}
|
|
|
|
static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
|
|
unsigned int offset)
|
|
{
|
|
WARN_ON(1);
|
|
}
|
|
#endif /* CONFIG_GPIOLIB */
|
|
|
|
#define for_each_gpiochip_node(dev, child) \
|
|
device_for_each_child_node(dev, child) \
|
|
if (!fwnode_property_present(child, "gpio-controller")) {} else
|
|
|
|
static inline unsigned int gpiochip_node_count(struct device *dev)
|
|
{
|
|
struct fwnode_handle *child;
|
|
unsigned int count = 0;
|
|
|
|
for_each_gpiochip_node(dev, child)
|
|
count++;
|
|
|
|
return count;
|
|
}
|
|
|
|
static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
|
|
{
|
|
struct fwnode_handle *fwnode;
|
|
|
|
for_each_gpiochip_node(dev, fwnode)
|
|
return fwnode;
|
|
|
|
return NULL;
|
|
}
|
|
|
|
#endif /* __LINUX_GPIO_DRIVER_H */
|