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2997e48716
1. Add support for AM64 SoC. 2. Minor improvement: use platform_get_irq(). -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmHFq0cQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD18wsD/0efj2Ex0um0R1w8RyesHbQZW3XNOApncRY 52vNV77QDtrgOwZpMIU0t+WW0vAqBQ9vXxZ8J/XtsyfkYHymGJLBzLClVeddXRv/ mOrnVYnNxpySRBDJnbzXge2w53U2mCnIJHe490/y3RlNKmxibvRUGcaR8egDaRmu JyIjKgMqC5S4D0/qIYm3EgvWG6t2bEHF3E/wAlbBaCZMFQgIu5+rEAKzfIbCBFPs O1EleSe56Tx8XVi47s0yB9bolWQabIx6+ED0hi6VsDiOJNgMaVaLbU1hzusO3pvv V5qLoXJnOVbyzNFmUpWUylplX8SImCdZl/U/T0KQsYihc74J1JjS6OBuBzXqNX93 w/uG5x5cXSEELWOU+WuhLzgfxCHDyT/bmRW/gTtgmvPa3xxphom1kJcmKjslp6Bi o8P/kvIdweixEM3EorOalD0ztX0q5eWNoJ/I9ObYNqgh3ls2BjyWzV5oe42/oFXE B24zmZuNHt5XAcATTGcTEjZCZCBWErdMTwZnIV7gXSh5p3kvDPSMwrqP+wFvNjyg O8Ifd1fqnIXVLtFVqN/mHbUfEyZrkjVcjxSBkb5p9nB2gtfa7BMJhvyA+rxZOBte MmKpVt9DFZ17I6mmAywXVVnMePut6bJ8Fqq6E4ewuza3aAOXB2i2nrDGcu75gn3k UEJ0ZwQCnQ== =eb46 -----END PGP SIGNATURE----- Merge tag 'memory-controller-drv-omap-5.17' into nand/next Memory controller drivers for v5.17 - OMAP GPMC 1. Add support for AM64 SoC. 2. Minor improvement: use platform_get_irq(). [miquel.raynal@bootlin.com: A first commit introduced a new omap compatible and another moved the IDs to a header which created a conflict: moving the new ID as well in the header fixed it.] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2006 Micron Technology Inc.
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*/
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#ifndef _MTD_NAND_OMAP2_H
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#define _MTD_NAND_OMAP2_H
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#include <linux/mtd/partitions.h>
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#include <linux/mod_devicetable.h>
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#define GPMC_BCH_NUM_REMAINDER 8
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enum nand_io {
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NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
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NAND_OMAP_POLLED, /* polled mode, without prefetch */
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NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
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NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
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};
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enum omap_ecc {
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/*
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* 1-bit ECC: calculation and correction by SW
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* ECC stored at end of spare area
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*/
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OMAP_ECC_HAM1_CODE_SW = 0,
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/*
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* 1-bit ECC: calculation by GPMC, Error detection by Software
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* ECC layout compatible with ROM code layout
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*/
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OMAP_ECC_HAM1_CODE_HW,
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/* 4-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
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/* 4-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH4_CODE_HW,
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/* 8-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
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/* 8-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH8_CODE_HW,
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/* 16-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH16_CODE_HW,
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};
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struct gpmc_nand_regs {
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void __iomem *gpmc_nand_command;
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void __iomem *gpmc_nand_address;
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void __iomem *gpmc_nand_data;
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void __iomem *gpmc_prefetch_config1;
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void __iomem *gpmc_prefetch_config2;
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void __iomem *gpmc_prefetch_control;
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void __iomem *gpmc_prefetch_status;
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void __iomem *gpmc_ecc_config;
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void __iomem *gpmc_ecc_control;
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void __iomem *gpmc_ecc_size_config;
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void __iomem *gpmc_ecc1_result;
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void __iomem *gpmc_bch_result0[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
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};
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static const struct of_device_id omap_nand_ids[] = {
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{ .compatible = "ti,omap2-nand", },
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{ .compatible = "ti,am64-nand", },
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{},
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};
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#endif /* _MTD_NAND_OMAP2_H */
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