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9b71e1c9c3
Recall that a CXL Port is any object that publishes a CXL HDM Decoder Capability structure. That is Host Bridge and Switches that have been enabled so far. Now, add decoder support to the 'endpoint' CXL Ports registered by the cxl_mem driver. They mostly share the same enumeration as Bridges and Switches, but witout a target list. The target of endpoint decode is device-internal DPA space, not another downstream port. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> [djbw: clarify changelog, hookup enumeration in the port driver] Link: https://lore.kernel.org/r/164386092069.765089.14895687988217608642.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
76 lines
2 KiB
C
76 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "cxlmem.h"
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#include "cxlpci.h"
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/**
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* DOC: cxl port
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*
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* The port driver enumerates dport via PCI and scans for HDM
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* (Host-managed-Device-Memory) decoder resources via the
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* @component_reg_phys value passed in by the agent that registered the
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* port. All descendant ports of a CXL root port (described by platform
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* firmware) are managed in this drivers context. Each driver instance
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* is responsible for tearing down the driver context of immediate
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* descendant ports. The locking for this is validated by
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* CONFIG_PROVE_CXL_LOCKING.
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*
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* The primary service this driver provides is presenting APIs to other
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* drivers to utilize the decoders, and indicating to userspace (via bind
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* status) the connectivity of the CXL.mem protocol throughout the
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* PCIe topology.
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*/
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static void schedule_detach(void *cxlmd)
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{
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schedule_cxl_memdev_detach(cxlmd);
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}
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static int cxl_port_probe(struct device *dev)
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{
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struct cxl_port *port = to_cxl_port(dev);
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struct cxl_hdm *cxlhdm;
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int rc;
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if (is_cxl_endpoint(port)) {
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struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
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get_device(&cxlmd->dev);
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rc = devm_add_action_or_reset(dev, schedule_detach, cxlmd);
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if (rc)
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return rc;
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} else {
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rc = devm_cxl_port_enumerate_dports(port);
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if (rc < 0)
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return rc;
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if (rc == 1)
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return devm_cxl_add_passthrough_decoder(port);
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}
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cxlhdm = devm_cxl_setup_hdm(port);
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if (IS_ERR(cxlhdm))
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return PTR_ERR(cxlhdm);
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rc = devm_cxl_enumerate_decoders(cxlhdm);
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if (rc) {
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dev_err(dev, "Couldn't enumerate decoders (%d)\n", rc);
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return rc;
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}
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return 0;
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}
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static struct cxl_driver cxl_port_driver = {
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.name = "cxl_port",
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.probe = cxl_port_probe,
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.id = CXL_DEVICE_PORT,
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};
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module_cxl_driver(cxl_port_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(CXL);
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MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
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