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d0c175da68
Move the register definitions into a separate header file to reflect the gxbb implementation. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-3-git-send-email-serveralex@gmail.com
40 lines
1.5 KiB
C
40 lines
1.5 KiB
C
/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* Copyright (c) 2016 BayLibre, Inc.
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* Michael Turquette <mturquette@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MESON8B_H
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#define __MESON8B_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the HardKernel[0] data sheet are listed in comment
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* blocks below. Those offsets must be multiplied by 4 before adding them to
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* the base address to get the right value
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
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#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
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#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
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#define MESON8B_REG_PLL_FIXED 0x0280
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#define MESON8B_REG_PLL_SYS 0x0300
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#define MESON8B_REG_PLL_VID 0x0320
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#endif /* __MESON8B_H */
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