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-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPERUPAAoJEEFnBt12D9kBIgkQAI5kJ6HhPMeuSWVN8RiuLxvY VsE77HffpdwCSVWjNqYLN132zkEkH7Bt/yxPp3om4ursh6qPL2tdxJZGJiBbt4iL pRtPCYvaH/JGeXlXA7C0k7ltJpiEK1aT/0GulrkiyvBUfqTQNPBZNUkA8VnTN/Xo Rsmg4Px3ECNIftS2xKsvdb70lZd9OHd5XCp6dv/7wAyPOxm8npBf7e/QwlBaUAzZ 6MxY4+5WFih+6+MioXdkIbIsmN2QIRyZ5RbJQpd6EHYpuzB875l2Cau06hzNL4vZ 8g/l4sRZ2fXdYqge6ZHEeaK23wkOigfi9xWQEjrhWDZVdOp7kaML8ZIIGXhnNMHR /5Hb6WcL0paGAiZHreFhdaof/eYuguVjXZAxAM6FeAiU3Zr88WDeWvbzakmPQVgg DNT3rnydaTaJRPV5gDjyv6mW/MuHjicCjJpgSYTDITy4FLKZGmZ9EgXtJV94RkKq 8Wk94ybX5nNM1N9uGH3Iau7R1VEie+xrfSPFtUTkqUMlimNAjTohNN9g4l/S8sDI /fWSEbfoI5vXIpbtfNLp9cp3OuDm8HqjLlWToHbsygPxQv+ZR8vK4J8ztW9OnDYt ybx53all5hhu+qdcu+LfdcdG4xEsjXgxvRaMFgRXQkHCQaqGgZTyQaV7Gw/+3YMs TNBFdyv1yxysAx8qKS+O =yG1E -----END PGP SIGNATURE----- Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6 2nd round of GPIO changes for v3.3 merge window * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6: GPIO: sa1100: implement proper gpiolib gpio_to_irq conversion gpio: pl061: remove combined interrupt gpio: pl061: convert to use generic irq chip GPIO: add bindings for managed devices ARM: realview: convert pl061 no irq to 0 instead of -1 gpio: pl061: convert to use 0 for no irq gpio: pl061: use chained_irq_* functions in irq handler GPIO/pl061: Add suspend resume capability drivers/gpio/gpio-tegra.c: use devm_request_and_ioremap
387 lines
9.2 KiB
C
387 lines
9.2 KiB
C
/*
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* Copyright (C) 2008, 2009 Provigent Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
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*
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* Data sheet: ARM DDI 0190B, September 2000
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*/
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <linux/workqueue.h>
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#include <linux/gpio.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl061.h>
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#include <linux/slab.h>
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#include <linux/pm.h>
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#include <asm/mach/irq.h>
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#define GPIODIR 0x400
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#define GPIOIS 0x404
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#define GPIOIBE 0x408
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#define GPIOIEV 0x40C
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#define GPIOIE 0x410
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#define GPIORIS 0x414
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#define GPIOMIS 0x418
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#define GPIOIC 0x41C
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#define PL061_GPIO_NR 8
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#ifdef CONFIG_PM
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struct pl061_context_save_regs {
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u8 gpio_data;
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u8 gpio_dir;
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u8 gpio_is;
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u8 gpio_ibe;
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u8 gpio_iev;
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u8 gpio_ie;
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};
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#endif
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struct pl061_gpio {
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/* Each of the two spinlocks protects a different set of hardware
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* regiters and data structurs. This decouples the code of the IRQ from
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* the GPIO code. This also makes the case of a GPIO routine call from
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* the IRQ code simpler.
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*/
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spinlock_t lock; /* GPIO registers */
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void __iomem *base;
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int irq_base;
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struct irq_chip_generic *irq_gc;
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struct gpio_chip gc;
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#ifdef CONFIG_PM
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struct pl061_context_save_regs csave_regs;
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#endif
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};
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static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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unsigned long flags;
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unsigned char gpiodir;
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if (offset >= gc->ngpio)
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return -EINVAL;
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spin_lock_irqsave(&chip->lock, flags);
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gpiodir = readb(chip->base + GPIODIR);
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gpiodir &= ~(1 << offset);
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writeb(gpiodir, chip->base + GPIODIR);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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unsigned long flags;
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unsigned char gpiodir;
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if (offset >= gc->ngpio)
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return -EINVAL;
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spin_lock_irqsave(&chip->lock, flags);
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writeb(!!value << offset, chip->base + (1 << (offset + 2)));
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gpiodir = readb(chip->base + GPIODIR);
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gpiodir |= 1 << offset;
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writeb(gpiodir, chip->base + GPIODIR);
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/*
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* gpio value is set again, because pl061 doesn't allow to set value of
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* a gpio pin before configuring it in OUT mode.
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*/
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writeb(!!value << offset, chip->base + (1 << (offset + 2)));
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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return !!readb(chip->base + (1 << (offset + 2)));
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}
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static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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writeb(!!value << offset, chip->base + (1 << (offset + 2)));
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}
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static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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if (chip->irq_base <= 0)
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return -EINVAL;
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return chip->irq_base + offset;
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}
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static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pl061_gpio *chip = gc->private;
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int offset = d->irq - chip->irq_base;
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unsigned long flags;
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u8 gpiois, gpioibe, gpioiev;
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if (offset < 0 || offset >= PL061_GPIO_NR)
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return -EINVAL;
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raw_spin_lock_irqsave(&gc->lock, flags);
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gpioiev = readb(chip->base + GPIOIEV);
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gpiois = readb(chip->base + GPIOIS);
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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gpiois |= 1 << offset;
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if (trigger & IRQ_TYPE_LEVEL_HIGH)
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gpioiev |= 1 << offset;
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else
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gpioiev &= ~(1 << offset);
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} else
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gpiois &= ~(1 << offset);
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writeb(gpiois, chip->base + GPIOIS);
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gpioibe = readb(chip->base + GPIOIBE);
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if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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gpioibe |= 1 << offset;
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else {
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gpioibe &= ~(1 << offset);
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if (trigger & IRQ_TYPE_EDGE_RISING)
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gpioiev |= 1 << offset;
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else if (trigger & IRQ_TYPE_EDGE_FALLING)
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gpioiev &= ~(1 << offset);
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}
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writeb(gpioibe, chip->base + GPIOIBE);
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writeb(gpioiev, chip->base + GPIOIEV);
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raw_spin_unlock_irqrestore(&gc->lock, flags);
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return 0;
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}
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static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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unsigned long pending;
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int offset;
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struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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chained_irq_enter(irqchip, desc);
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pending = readb(chip->base + GPIOMIS);
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writeb(pending, chip->base + GPIOIC);
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if (pending) {
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for_each_set_bit(offset, &pending, PL061_GPIO_NR)
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generic_handle_irq(pl061_to_irq(&chip->gc, offset));
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}
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chained_irq_exit(irqchip, desc);
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}
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static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
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{
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struct irq_chip_type *ct;
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chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
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chip->base, handle_simple_irq);
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chip->irq_gc->private = chip;
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ct = chip->irq_gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = pl061_irq_type;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->regs.mask = GPIOIE;
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irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
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IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
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}
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static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
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{
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struct pl061_platform_data *pdata;
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struct pl061_gpio *chip;
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int ret, irq, i;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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return -ENOMEM;
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pdata = dev->dev.platform_data;
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if (pdata) {
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chip->gc.base = pdata->gpio_base;
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chip->irq_base = pdata->irq_base;
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} else if (dev->dev.of_node) {
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chip->gc.base = -1;
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chip->irq_base = 0;
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} else {
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ret = -ENODEV;
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goto free_mem;
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}
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if (!request_mem_region(dev->res.start,
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resource_size(&dev->res), "pl061")) {
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ret = -EBUSY;
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goto free_mem;
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}
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chip->base = ioremap(dev->res.start, resource_size(&dev->res));
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if (chip->base == NULL) {
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ret = -ENOMEM;
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goto release_region;
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}
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spin_lock_init(&chip->lock);
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chip->gc.direction_input = pl061_direction_input;
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chip->gc.direction_output = pl061_direction_output;
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chip->gc.get = pl061_get_value;
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chip->gc.set = pl061_set_value;
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chip->gc.to_irq = pl061_to_irq;
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chip->gc.ngpio = PL061_GPIO_NR;
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chip->gc.label = dev_name(&dev->dev);
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chip->gc.dev = &dev->dev;
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chip->gc.owner = THIS_MODULE;
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ret = gpiochip_add(&chip->gc);
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if (ret)
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goto iounmap;
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/*
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* irq_chip support
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*/
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if (chip->irq_base <= 0)
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return 0;
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pl061_init_gc(chip, chip->irq_base);
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writeb(0, chip->base + GPIOIE); /* disable irqs */
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irq = dev->irq[0];
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if (irq < 0) {
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ret = -ENODEV;
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goto iounmap;
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}
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irq_set_chained_handler(irq, pl061_irq_handler);
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irq_set_handler_data(irq, chip);
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for (i = 0; i < PL061_GPIO_NR; i++) {
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if (pdata) {
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if (pdata->directions & (1 << i))
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pl061_direction_output(&chip->gc, i,
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pdata->values & (1 << i));
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else
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pl061_direction_input(&chip->gc, i);
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}
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}
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amba_set_drvdata(dev, chip);
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return 0;
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iounmap:
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iounmap(chip->base);
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release_region:
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release_mem_region(dev->res.start, resource_size(&dev->res));
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free_mem:
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kfree(chip);
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return ret;
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}
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#ifdef CONFIG_PM
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static int pl061_suspend(struct device *dev)
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{
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struct pl061_gpio *chip = dev_get_drvdata(dev);
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int offset;
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chip->csave_regs.gpio_data = 0;
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chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
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chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
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chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
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chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
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chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
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for (offset = 0; offset < PL061_GPIO_NR; offset++) {
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if (chip->csave_regs.gpio_dir & (1 << offset))
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chip->csave_regs.gpio_data |=
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pl061_get_value(&chip->gc, offset) << offset;
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}
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return 0;
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}
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static int pl061_resume(struct device *dev)
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{
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struct pl061_gpio *chip = dev_get_drvdata(dev);
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int offset;
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for (offset = 0; offset < PL061_GPIO_NR; offset++) {
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if (chip->csave_regs.gpio_dir & (1 << offset))
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pl061_direction_output(&chip->gc, offset,
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chip->csave_regs.gpio_data &
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(1 << offset));
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else
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pl061_direction_input(&chip->gc, offset);
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}
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writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
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writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
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writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
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writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_resume);
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#endif
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static struct amba_id pl061_ids[] = {
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{
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.id = 0x00041061,
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.mask = 0x000fffff,
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},
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{ 0, 0 },
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};
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MODULE_DEVICE_TABLE(amba, pl061_ids);
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static struct amba_driver pl061_gpio_driver = {
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.drv = {
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.name = "pl061_gpio",
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#ifdef CONFIG_PM
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.pm = &pl061_dev_pm_ops,
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#endif
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},
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.id_table = pl061_ids,
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.probe = pl061_probe,
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};
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static int __init pl061_gpio_init(void)
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{
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return amba_driver_register(&pl061_gpio_driver);
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}
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subsys_initcall(pl061_gpio_init);
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MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
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MODULE_DESCRIPTION("PL061 GPIO driver");
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MODULE_LICENSE("GPL");
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