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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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e53d28180d
This patch adds support for kdump, the kernel will reserve a region for the crash kernel and jump there on panic. In order for userspace tools (kexec-tools) to prepare the crash kernel kexec image, we also need to expose some information on /proc/iomem for the memory regions used by the kernel and for the region reserved for crash kernel. Note that on userspace the device tree is used to determine the system's memory layout so the "System RAM" on /proc/iomem is ignored. I tested this on riscv64 qemu and works as expected, you may test it by triggering a crash through /proc/sysrq_trigger: echo c > /proc/sysrq_trigger Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
56 lines
1.6 KiB
ArmAsm
56 lines
1.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 FORTH-ICS/CARV
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#include <asm/asm.h> /* For RISCV_* and REG_* macros */
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#include <asm/csr.h> /* For CSR_* macros */
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#include <asm/asm-offsets.h> /* For offsets on pt_regs */
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#include <linux/linkage.h> /* For SYM_* macros */
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.section ".text"
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SYM_CODE_START(riscv_crash_save_regs)
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REG_S ra, PT_RA(a0) /* x1 */
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REG_S sp, PT_SP(a0) /* x2 */
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REG_S gp, PT_GP(a0) /* x3 */
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REG_S tp, PT_TP(a0) /* x4 */
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REG_S t0, PT_T0(a0) /* x5 */
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REG_S t1, PT_T1(a0) /* x6 */
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REG_S t2, PT_T2(a0) /* x7 */
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REG_S s0, PT_S0(a0) /* x8/fp */
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REG_S s1, PT_S1(a0) /* x9 */
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REG_S a0, PT_A0(a0) /* x10 */
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REG_S a1, PT_A1(a0) /* x11 */
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REG_S a2, PT_A2(a0) /* x12 */
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REG_S a3, PT_A3(a0) /* x13 */
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REG_S a4, PT_A4(a0) /* x14 */
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REG_S a5, PT_A5(a0) /* x15 */
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REG_S a6, PT_A6(a0) /* x16 */
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REG_S a7, PT_A7(a0) /* x17 */
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REG_S s2, PT_S2(a0) /* x18 */
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REG_S s3, PT_S3(a0) /* x19 */
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REG_S s4, PT_S4(a0) /* x20 */
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REG_S s5, PT_S5(a0) /* x21 */
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REG_S s6, PT_S6(a0) /* x22 */
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REG_S s7, PT_S7(a0) /* x23 */
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REG_S s8, PT_S8(a0) /* x24 */
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REG_S s9, PT_S9(a0) /* x25 */
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REG_S s10, PT_S10(a0) /* x26 */
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REG_S s11, PT_S11(a0) /* x27 */
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REG_S t3, PT_T3(a0) /* x28 */
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REG_S t4, PT_T4(a0) /* x29 */
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REG_S t5, PT_T5(a0) /* x30 */
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REG_S t6, PT_T6(a0) /* x31 */
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csrr t1, CSR_STATUS
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csrr t2, CSR_EPC
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csrr t3, CSR_TVAL
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csrr t4, CSR_CAUSE
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REG_S t1, PT_STATUS(a0)
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REG_S t2, PT_EPC(a0)
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REG_S t3, PT_BADADDR(a0)
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REG_S t4, PT_CAUSE(a0)
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ret
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SYM_CODE_END(riscv_crash_save_regs)
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