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a0701b6263
Add core support for the NXP fxas21002c Tri-axis gyroscope, using the iio subsystem. It supports PM operations, axis reading, temperature, scale factor of the axis, high pass and low pass filtering, and sampling frequency selection. It will have extras modules to support the communication over i2c and spi. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
150 lines
5.6 KiB
C
150 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Driver for NXP FXAS21002C Gyroscope - Header
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*
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* Copyright (C) 2019 Linaro Ltd.
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*/
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#ifndef FXAS21002C_H_
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#define FXAS21002C_H_
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#include <linux/regmap.h>
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#define FXAS21002C_REG_STATUS 0x00
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#define FXAS21002C_REG_OUT_X_MSB 0x01
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#define FXAS21002C_REG_OUT_X_LSB 0x02
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#define FXAS21002C_REG_OUT_Y_MSB 0x03
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#define FXAS21002C_REG_OUT_Y_LSB 0x04
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#define FXAS21002C_REG_OUT_Z_MSB 0x05
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#define FXAS21002C_REG_OUT_Z_LSB 0x06
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#define FXAS21002C_REG_DR_STATUS 0x07
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#define FXAS21002C_REG_F_STATUS 0x08
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#define FXAS21002C_REG_F_SETUP 0x09
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#define FXAS21002C_REG_F_EVENT 0x0A
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#define FXAS21002C_REG_INT_SRC_FLAG 0x0B
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#define FXAS21002C_REG_WHO_AM_I 0x0C
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#define FXAS21002C_REG_CTRL0 0x0D
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#define FXAS21002C_REG_RT_CFG 0x0E
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#define FXAS21002C_REG_RT_SRC 0x0F
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#define FXAS21002C_REG_RT_THS 0x10
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#define FXAS21002C_REG_RT_COUNT 0x11
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#define FXAS21002C_REG_TEMP 0x12
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#define FXAS21002C_REG_CTRL1 0x13
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#define FXAS21002C_REG_CTRL2 0x14
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#define FXAS21002C_REG_CTRL3 0x15
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enum fxas21002c_fields {
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F_DR_STATUS,
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F_OUT_X_MSB,
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F_OUT_X_LSB,
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F_OUT_Y_MSB,
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F_OUT_Y_LSB,
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F_OUT_Z_MSB,
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F_OUT_Z_LSB,
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/* DR_STATUS */
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F_ZYX_OW, F_Z_OW, F_Y_OW, F_X_OW, F_ZYX_DR, F_Z_DR, F_Y_DR, F_X_DR,
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/* F_STATUS */
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F_OVF, F_WMKF, F_CNT,
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/* F_SETUP */
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F_MODE, F_WMRK,
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/* F_EVENT */
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F_EVENT, FE_TIME,
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/* INT_SOURCE_FLAG */
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F_BOOTEND, F_SRC_FIFO, F_SRC_RT, F_SRC_DRDY,
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/* WHO_AM_I */
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F_WHO_AM_I,
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/* CTRL_REG0 */
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F_BW, F_SPIW, F_SEL, F_HPF_EN, F_FS,
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/* RT_CFG */
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F_ELE, F_ZTEFE, F_YTEFE, F_XTEFE,
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/* RT_SRC */
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F_EA, F_ZRT, F_ZRT_POL, F_YRT, F_YRT_POL, F_XRT, F_XRT_POL,
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/* RT_THS */
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F_DBCNTM, F_THS,
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/* RT_COUNT */
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F_RT_COUNT,
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/* TEMP */
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F_TEMP,
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/* CTRL_REG1 */
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F_RST, F_ST, F_DR, F_ACTIVE, F_READY,
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/* CTRL_REG2 */
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F_INT_CFG_FIFO, F_INT_EN_FIFO, F_INT_CFG_RT, F_INT_EN_RT,
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F_INT_CFG_DRDY, F_INT_EN_DRDY, F_IPOL, F_PP_OD,
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/* CTRL_REG3 */
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F_WRAPTOONE, F_EXTCTRLEN, F_FS_DOUBLE,
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/* MAX FIELDS */
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F_MAX_FIELDS,
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};
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static const struct reg_field fxas21002c_reg_fields[] = {
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[F_DR_STATUS] = REG_FIELD(FXAS21002C_REG_STATUS, 0, 7),
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[F_OUT_X_MSB] = REG_FIELD(FXAS21002C_REG_OUT_X_MSB, 0, 7),
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[F_OUT_X_LSB] = REG_FIELD(FXAS21002C_REG_OUT_X_LSB, 0, 7),
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[F_OUT_Y_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_MSB, 0, 7),
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[F_OUT_Y_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_LSB, 0, 7),
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[F_OUT_Z_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_MSB, 0, 7),
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[F_OUT_Z_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_LSB, 0, 7),
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[F_ZYX_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 7, 7),
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[F_Z_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 6, 6),
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[F_Y_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 5, 5),
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[F_X_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 4, 4),
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[F_ZYX_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 3, 3),
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[F_Z_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 2, 2),
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[F_Y_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 1, 1),
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[F_X_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 0, 0),
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[F_OVF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 7, 7),
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[F_WMKF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 6, 6),
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[F_CNT] = REG_FIELD(FXAS21002C_REG_F_STATUS, 0, 5),
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[F_MODE] = REG_FIELD(FXAS21002C_REG_F_SETUP, 6, 7),
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[F_WMRK] = REG_FIELD(FXAS21002C_REG_F_SETUP, 0, 5),
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[F_EVENT] = REG_FIELD(FXAS21002C_REG_F_EVENT, 5, 5),
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[FE_TIME] = REG_FIELD(FXAS21002C_REG_F_EVENT, 0, 4),
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[F_BOOTEND] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 3, 3),
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[F_SRC_FIFO] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 2, 2),
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[F_SRC_RT] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 1, 1),
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[F_SRC_DRDY] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 0, 0),
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[F_WHO_AM_I] = REG_FIELD(FXAS21002C_REG_WHO_AM_I, 0, 7),
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[F_BW] = REG_FIELD(FXAS21002C_REG_CTRL0, 6, 7),
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[F_SPIW] = REG_FIELD(FXAS21002C_REG_CTRL0, 5, 5),
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[F_SEL] = REG_FIELD(FXAS21002C_REG_CTRL0, 3, 4),
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[F_HPF_EN] = REG_FIELD(FXAS21002C_REG_CTRL0, 2, 2),
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[F_FS] = REG_FIELD(FXAS21002C_REG_CTRL0, 0, 1),
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[F_ELE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 3, 3),
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[F_ZTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 2, 2),
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[F_YTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 1, 1),
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[F_XTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 0, 0),
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[F_EA] = REG_FIELD(FXAS21002C_REG_RT_SRC, 6, 6),
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[F_ZRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 5, 5),
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[F_ZRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 4, 4),
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[F_YRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 3, 3),
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[F_YRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 2, 2),
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[F_XRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 1, 1),
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[F_XRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 0),
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[F_DBCNTM] = REG_FIELD(FXAS21002C_REG_RT_THS, 7, 7),
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[F_THS] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 6),
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[F_RT_COUNT] = REG_FIELD(FXAS21002C_REG_RT_COUNT, 0, 7),
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[F_TEMP] = REG_FIELD(FXAS21002C_REG_TEMP, 0, 7),
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[F_RST] = REG_FIELD(FXAS21002C_REG_CTRL1, 6, 6),
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[F_ST] = REG_FIELD(FXAS21002C_REG_CTRL1, 5, 5),
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[F_DR] = REG_FIELD(FXAS21002C_REG_CTRL1, 2, 4),
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[F_ACTIVE] = REG_FIELD(FXAS21002C_REG_CTRL1, 1, 1),
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[F_READY] = REG_FIELD(FXAS21002C_REG_CTRL1, 0, 0),
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[F_INT_CFG_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 7, 7),
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[F_INT_EN_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 6, 6),
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[F_INT_CFG_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 5, 5),
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[F_INT_EN_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 4, 4),
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[F_INT_CFG_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 3, 3),
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[F_INT_EN_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 2, 2),
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[F_IPOL] = REG_FIELD(FXAS21002C_REG_CTRL2, 1, 1),
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[F_PP_OD] = REG_FIELD(FXAS21002C_REG_CTRL2, 0, 0),
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[F_WRAPTOONE] = REG_FIELD(FXAS21002C_REG_CTRL3, 3, 3),
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[F_EXTCTRLEN] = REG_FIELD(FXAS21002C_REG_CTRL3, 2, 2),
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[F_FS_DOUBLE] = REG_FIELD(FXAS21002C_REG_CTRL3, 0, 0),
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};
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extern const struct dev_pm_ops fxas21002c_pm_ops;
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int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq,
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const char *name);
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void fxas21002c_core_remove(struct device *dev);
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#endif
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