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![Anton Vorontsov](/assets/img/avatar_default.png)
Since we renamed the file, we might want to rename the file internals too. Though we don't bother with changing platform driver name and platform module alias. The stuff is legacy and hopefully we'll remove it soon. Suggested-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Cc: David Brownell <david-b@pacbell.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
945 lines
22 KiB
C
945 lines
22 KiB
C
/*
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* MPC8xxx SPI controller driver.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright (C) 2006 Polycom, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_devices.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <linux/of_spi.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/irq.h>
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/* SPI Controller registers */
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struct mpc8xxx_spi_reg {
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u8 res1[0x20];
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__be32 mode;
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__be32 event;
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__be32 mask;
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__be32 command;
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__be32 transmit;
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__be32 receive;
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};
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/* SPI Controller mode register definitions */
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#define SPMODE_LOOP (1 << 30)
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#define SPMODE_CI_INACTIVEHIGH (1 << 29)
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#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
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#define SPMODE_DIV16 (1 << 27)
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#define SPMODE_REV (1 << 26)
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#define SPMODE_MS (1 << 25)
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#define SPMODE_ENABLE (1 << 24)
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#define SPMODE_LEN(x) ((x) << 20)
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#define SPMODE_PM(x) ((x) << 16)
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#define SPMODE_OP (1 << 14)
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#define SPMODE_CG(x) ((x) << 7)
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/*
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* Default for SPI Mode:
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* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
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*/
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#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
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SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
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/* SPIE register values */
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#define SPIE_NE 0x00000200 /* Not empty */
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#define SPIE_NF 0x00000100 /* Not full */
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/* SPIM register values */
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#define SPIM_NE 0x00000200 /* Not empty */
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#define SPIM_NF 0x00000100 /* Not full */
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/* SPI Controller driver's private data. */
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struct mpc8xxx_spi {
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struct mpc8xxx_spi_reg __iomem *base;
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/* rx & tx bufs from the spi_transfer */
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const void *tx;
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void *rx;
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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u32(*get_tx) (struct mpc8xxx_spi *);
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unsigned int count;
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unsigned int irq;
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unsigned nsecs; /* (clock cycle time)/2 */
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u32 spibrg; /* SPIBRG input clock */
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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bool qe_mode;
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struct workqueue_struct *workqueue;
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struct work_struct work;
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struct list_head queue;
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spinlock_t lock;
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struct completion done;
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};
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struct spi_mpc8xxx_cs {
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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u32 (*get_tx) (struct mpc8xxx_spi *);
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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u32 hw_mode; /* Holds HW mode register settings */
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};
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static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
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{
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out_be32(reg, val);
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}
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static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
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{
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return in_be32(reg);
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}
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#define MPC83XX_SPI_RX_BUF(type) \
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static \
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void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
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{ \
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type *rx = mpc8xxx_spi->rx; \
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*rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
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mpc8xxx_spi->rx = rx; \
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}
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#define MPC83XX_SPI_TX_BUF(type) \
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static \
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u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
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{ \
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u32 data; \
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const type *tx = mpc8xxx_spi->tx; \
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if (!tx) \
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return 0; \
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data = *tx++ << mpc8xxx_spi->tx_shift; \
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mpc8xxx_spi->tx = tx; \
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return data; \
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}
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MPC83XX_SPI_RX_BUF(u8)
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MPC83XX_SPI_RX_BUF(u16)
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MPC83XX_SPI_RX_BUF(u32)
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MPC83XX_SPI_TX_BUF(u8)
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MPC83XX_SPI_TX_BUF(u16)
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MPC83XX_SPI_TX_BUF(u32)
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static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
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bool pol = spi->mode & SPI_CS_HIGH;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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if (value == BITBANG_CS_INACTIVE) {
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if (pdata->cs_control)
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pdata->cs_control(spi, !pol);
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}
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if (value == BITBANG_CS_ACTIVE) {
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u32 regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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if (cs->hw_mode != regval) {
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unsigned long flags;
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__be32 __iomem *mode = &mpc8xxx_spi->base->mode;
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regval = cs->hw_mode;
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/* Turn off IRQs locally to minimize time that
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* SPI is disabled
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*/
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
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mpc8xxx_spi_write_reg(mode, regval);
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local_irq_restore(flags);
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}
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if (pdata->cs_control)
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pdata->cs_control(spi, pol);
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}
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}
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static
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int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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u32 regval;
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u8 bits_per_word, pm;
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u32 hz;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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if (t) {
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bits_per_word = t->bits_per_word;
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hz = t->speed_hz;
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} else {
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bits_per_word = 0;
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hz = 0;
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}
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/* spi_transfer level calls that work per-word */
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if (!bits_per_word)
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bits_per_word = spi->bits_per_word;
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/* Make sure its a bit width we support [4..16, 32] */
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if ((bits_per_word < 4)
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|| ((bits_per_word > 16) && (bits_per_word != 32)))
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return -EINVAL;
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if (!hz)
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hz = spi->max_speed_hz;
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cs->rx_shift = 0;
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cs->tx_shift = 0;
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if (bits_per_word <= 8) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u8;
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cs->get_tx = mpc8xxx_spi_tx_buf_u8;
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if (mpc8xxx_spi->qe_mode) {
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cs->rx_shift = 16;
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cs->tx_shift = 24;
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}
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} else if (bits_per_word <= 16) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u16;
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cs->get_tx = mpc8xxx_spi_tx_buf_u16;
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if (mpc8xxx_spi->qe_mode) {
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cs->rx_shift = 16;
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cs->tx_shift = 16;
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}
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} else if (bits_per_word <= 32) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u32;
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cs->get_tx = mpc8xxx_spi_tx_buf_u32;
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} else
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return -EINVAL;
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if (mpc8xxx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
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cs->tx_shift = 0;
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if (bits_per_word <= 8)
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cs->rx_shift = 8;
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else
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cs->rx_shift = 0;
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}
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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if (bits_per_word == 32)
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bits_per_word = 0;
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else
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bits_per_word = bits_per_word - 1;
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
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| SPMODE_PM(0xF));
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cs->hw_mode |= SPMODE_LEN(bits_per_word);
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if ((mpc8xxx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= SPMODE_DIV16;
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pm = mpc8xxx_spi->spibrg / (hz * 64);
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WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
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"Will use %d Hz instead.\n", dev_name(&spi->dev),
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hz, mpc8xxx_spi->spibrg / 1024);
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if (pm > 16)
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pm = 16;
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} else
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pm = mpc8xxx_spi->spibrg / (hz * 4);
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if (pm)
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pm--;
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cs->hw_mode |= SPMODE_PM(pm);
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regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
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if (cs->hw_mode != regval) {
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unsigned long flags;
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__be32 __iomem *mode = &mpc8xxx_spi->base->mode;
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regval = cs->hw_mode;
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/* Turn off IRQs locally to minimize time
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* that SPI is disabled
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*/
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
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mpc8xxx_spi_write_reg(mode, regval);
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local_irq_restore(flags);
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}
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return 0;
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}
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static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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u32 word, len, bits_per_word;
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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mpc8xxx_spi->tx = t->tx_buf;
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mpc8xxx_spi->rx = t->rx_buf;
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bits_per_word = spi->bits_per_word;
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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len = t->len;
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if (bits_per_word > 8) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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if (bits_per_word > 16) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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mpc8xxx_spi->count = len;
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INIT_COMPLETION(mpc8xxx_spi->done);
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/* enable rx ints */
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE);
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/* transmit word */
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word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
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wait_for_completion(&mpc8xxx_spi->done);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
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return mpc8xxx_spi->count;
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}
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static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
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{
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struct spi_device *spi = m->spi;
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struct spi_transfer *t;
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unsigned int cs_change;
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const int nsecs = 50;
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int status;
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cs_change = 1;
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status = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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/* Don't allow changes if CS is active */
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status = -EINVAL;
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if (cs_change)
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status = mpc8xxx_spi_setup_transfer(spi, t);
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if (status < 0)
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break;
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}
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if (cs_change) {
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mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
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ndelay(nsecs);
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}
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cs_change = t->cs_change;
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if (t->len)
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status = mpc8xxx_spi_bufs(spi, t);
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if (status) {
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status = -EMSGSIZE;
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break;
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}
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m->actual_length += t->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (cs_change) {
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ndelay(nsecs);
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mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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}
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}
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m->status = status;
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m->complete(m->context);
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if (status || !cs_change) {
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ndelay(nsecs);
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mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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}
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mpc8xxx_spi_setup_transfer(spi, NULL);
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}
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static void mpc8xxx_spi_work(struct work_struct *work)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
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work);
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spin_lock_irq(&mpc8xxx_spi->lock);
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while (!list_empty(&mpc8xxx_spi->queue)) {
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struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
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struct spi_message, queue);
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list_del_init(&m->queue);
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spin_unlock_irq(&mpc8xxx_spi->lock);
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mpc8xxx_spi_do_one_msg(m);
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spin_lock_irq(&mpc8xxx_spi->lock);
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}
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spin_unlock_irq(&mpc8xxx_spi->lock);
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}
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static int mpc8xxx_spi_setup(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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int retval;
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u32 hw_mode;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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if (!spi->max_speed_hz)
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return -EINVAL;
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if (!cs) {
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cs = kzalloc(sizeof *cs, GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi->controller_state = cs;
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}
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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hw_mode = cs->hw_mode; /* Save orginal settings */
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cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
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| SPMODE_REV | SPMODE_LOOP);
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if (spi->mode & SPI_CPHA)
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cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
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if (spi->mode & SPI_CPOL)
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cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
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if (!(spi->mode & SPI_LSB_FIRST))
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cs->hw_mode |= SPMODE_REV;
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if (spi->mode & SPI_LOOP)
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cs->hw_mode |= SPMODE_LOOP;
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retval = mpc8xxx_spi_setup_transfer(spi, NULL);
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if (retval < 0) {
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cs->hw_mode = hw_mode; /* Restore settings */
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return retval;
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}
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return 0;
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}
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static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = context_data;
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u32 event;
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irqreturn_t ret = IRQ_NONE;
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/* Get interrupt events(tx/rx) */
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event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event);
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|
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/* We need handle RX first */
|
|
if (event & SPIE_NE) {
|
|
u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive);
|
|
|
|
if (mpc8xxx_spi->rx)
|
|
mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi);
|
|
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
if ((event & SPIE_NF) == 0)
|
|
/* spin until TX is done */
|
|
while (((event =
|
|
mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) &
|
|
SPIE_NF) == 0)
|
|
cpu_relax();
|
|
|
|
mpc8xxx_spi->count -= 1;
|
|
if (mpc8xxx_spi->count) {
|
|
u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
|
|
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
|
|
} else {
|
|
complete(&mpc8xxx_spi->done);
|
|
}
|
|
|
|
/* Clear the events */
|
|
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event);
|
|
|
|
return ret;
|
|
}
|
|
static int mpc8xxx_spi_transfer(struct spi_device *spi,
|
|
struct spi_message *m)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
|
|
unsigned long flags;
|
|
|
|
m->actual_length = 0;
|
|
m->status = -EINPROGRESS;
|
|
|
|
spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
|
|
list_add_tail(&m->queue, &mpc8xxx_spi->queue);
|
|
queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
|
|
spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static void mpc8xxx_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
kfree(spi->controller_state);
|
|
}
|
|
|
|
static struct spi_master * __devinit
|
|
mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev->platform_data;
|
|
struct spi_master *master;
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
u32 regval;
|
|
int ret = 0;
|
|
|
|
master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
|
|
if (master == NULL) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
dev_set_drvdata(dev, master);
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
|
|
| SPI_LSB_FIRST | SPI_LOOP;
|
|
|
|
master->setup = mpc8xxx_spi_setup;
|
|
master->transfer = mpc8xxx_spi_transfer;
|
|
master->cleanup = mpc8xxx_spi_cleanup;
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
mpc8xxx_spi->qe_mode = pdata->qe_mode;
|
|
mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
|
|
mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
|
|
mpc8xxx_spi->spibrg = pdata->sysclk;
|
|
|
|
mpc8xxx_spi->rx_shift = 0;
|
|
mpc8xxx_spi->tx_shift = 0;
|
|
if (mpc8xxx_spi->qe_mode) {
|
|
mpc8xxx_spi->rx_shift = 16;
|
|
mpc8xxx_spi->tx_shift = 24;
|
|
}
|
|
|
|
init_completion(&mpc8xxx_spi->done);
|
|
|
|
mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
|
|
if (mpc8xxx_spi->base == NULL) {
|
|
ret = -ENOMEM;
|
|
goto put_master;
|
|
}
|
|
|
|
mpc8xxx_spi->irq = irq;
|
|
|
|
/* Register for SPI Interrupt */
|
|
ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
|
|
0, "mpc8xxx_spi", mpc8xxx_spi);
|
|
|
|
if (ret != 0)
|
|
goto unmap_io;
|
|
|
|
master->bus_num = pdata->bus_num;
|
|
master->num_chipselect = pdata->max_chipselect;
|
|
|
|
/* SPI controller initializations */
|
|
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
|
|
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
|
|
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
|
|
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
|
|
|
|
/* Enable SPI interface */
|
|
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
|
|
if (pdata->qe_mode)
|
|
regval |= SPMODE_OP;
|
|
|
|
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
|
|
spin_lock_init(&mpc8xxx_spi->lock);
|
|
init_completion(&mpc8xxx_spi->done);
|
|
INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
|
|
INIT_LIST_HEAD(&mpc8xxx_spi->queue);
|
|
|
|
mpc8xxx_spi->workqueue = create_singlethread_workqueue(
|
|
dev_name(master->dev.parent));
|
|
if (mpc8xxx_spi->workqueue == NULL) {
|
|
ret = -EBUSY;
|
|
goto free_irq;
|
|
}
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret < 0)
|
|
goto unreg_master;
|
|
|
|
printk(KERN_INFO
|
|
"%s: MPC8xxx SPI Controller driver at 0x%p (irq = %d)\n",
|
|
dev_name(dev), mpc8xxx_spi->base, mpc8xxx_spi->irq);
|
|
|
|
return master;
|
|
|
|
unreg_master:
|
|
destroy_workqueue(mpc8xxx_spi->workqueue);
|
|
free_irq:
|
|
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
|
|
unmap_io:
|
|
iounmap(mpc8xxx_spi->base);
|
|
put_master:
|
|
spi_master_put(master);
|
|
err:
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static int __devexit mpc8xxx_spi_remove(struct device *dev)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct spi_master *master;
|
|
|
|
master = dev_get_drvdata(dev);
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
|
|
flush_workqueue(mpc8xxx_spi->workqueue);
|
|
destroy_workqueue(mpc8xxx_spi->workqueue);
|
|
spi_unregister_master(master);
|
|
|
|
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
|
|
iounmap(mpc8xxx_spi->base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct mpc8xxx_spi_probe_info {
|
|
struct fsl_spi_platform_data pdata;
|
|
int *gpios;
|
|
bool *alow_flags;
|
|
};
|
|
|
|
static struct mpc8xxx_spi_probe_info *
|
|
to_of_pinfo(struct fsl_spi_platform_data *pdata)
|
|
{
|
|
return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
|
|
}
|
|
|
|
static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
|
|
{
|
|
struct device *dev = spi->dev.parent;
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
|
|
u16 cs = spi->chip_select;
|
|
int gpio = pinfo->gpios[cs];
|
|
bool alow = pinfo->alow_flags[cs];
|
|
|
|
gpio_set_value(gpio, on ^ alow);
|
|
}
|
|
|
|
static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
|
|
{
|
|
struct device_node *np = dev_archdata_get_node(&dev->archdata);
|
|
struct fsl_spi_platform_data *pdata = dev->platform_data;
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
|
|
unsigned int ngpios;
|
|
int i = 0;
|
|
int ret;
|
|
|
|
ngpios = of_gpio_count(np);
|
|
if (!ngpios) {
|
|
/*
|
|
* SPI w/o chip-select line. One SPI device is still permitted
|
|
* though.
|
|
*/
|
|
pdata->max_chipselect = 1;
|
|
return 0;
|
|
}
|
|
|
|
pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
|
|
if (!pinfo->gpios)
|
|
return -ENOMEM;
|
|
memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
|
|
|
|
pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
|
|
GFP_KERNEL);
|
|
if (!pinfo->alow_flags) {
|
|
ret = -ENOMEM;
|
|
goto err_alloc_flags;
|
|
}
|
|
|
|
for (; i < ngpios; i++) {
|
|
int gpio;
|
|
enum of_gpio_flags flags;
|
|
|
|
gpio = of_get_gpio_flags(np, i, &flags);
|
|
if (!gpio_is_valid(gpio)) {
|
|
dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
|
|
goto err_loop;
|
|
}
|
|
|
|
ret = gpio_request(gpio, dev_name(dev));
|
|
if (ret) {
|
|
dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
|
|
goto err_loop;
|
|
}
|
|
|
|
pinfo->gpios[i] = gpio;
|
|
pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
|
|
|
|
ret = gpio_direction_output(pinfo->gpios[i],
|
|
pinfo->alow_flags[i]);
|
|
if (ret) {
|
|
dev_err(dev, "can't set output direction for gpio "
|
|
"#%d: %d\n", i, ret);
|
|
goto err_loop;
|
|
}
|
|
}
|
|
|
|
pdata->max_chipselect = ngpios;
|
|
pdata->cs_control = mpc8xxx_spi_cs_control;
|
|
|
|
return 0;
|
|
|
|
err_loop:
|
|
while (i >= 0) {
|
|
if (gpio_is_valid(pinfo->gpios[i]))
|
|
gpio_free(pinfo->gpios[i]);
|
|
i--;
|
|
}
|
|
|
|
kfree(pinfo->alow_flags);
|
|
pinfo->alow_flags = NULL;
|
|
err_alloc_flags:
|
|
kfree(pinfo->gpios);
|
|
pinfo->gpios = NULL;
|
|
return ret;
|
|
}
|
|
|
|
static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev->platform_data;
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
|
|
int i;
|
|
|
|
if (!pinfo->gpios)
|
|
return 0;
|
|
|
|
for (i = 0; i < pdata->max_chipselect; i++) {
|
|
if (gpio_is_valid(pinfo->gpios[i]))
|
|
gpio_free(pinfo->gpios[i]);
|
|
}
|
|
|
|
kfree(pinfo->gpios);
|
|
kfree(pinfo->alow_flags);
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
|
|
const struct of_device_id *ofid)
|
|
{
|
|
struct device *dev = &ofdev->dev;
|
|
struct device_node *np = ofdev->node;
|
|
struct mpc8xxx_spi_probe_info *pinfo;
|
|
struct fsl_spi_platform_data *pdata;
|
|
struct spi_master *master;
|
|
struct resource mem;
|
|
struct resource irq;
|
|
const void *prop;
|
|
int ret = -ENOMEM;
|
|
|
|
pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
|
|
if (!pinfo)
|
|
return -ENOMEM;
|
|
|
|
pdata = &pinfo->pdata;
|
|
dev->platform_data = pdata;
|
|
|
|
/* Allocate bus num dynamically. */
|
|
pdata->bus_num = -1;
|
|
|
|
/* SPI controller is either clocked from QE or SoC clock. */
|
|
pdata->sysclk = get_brgfreq();
|
|
if (pdata->sysclk == -1) {
|
|
pdata->sysclk = fsl_get_sys_freq();
|
|
if (pdata->sysclk == -1) {
|
|
ret = -ENODEV;
|
|
goto err_clk;
|
|
}
|
|
}
|
|
|
|
prop = of_get_property(np, "mode", NULL);
|
|
if (prop && !strcmp(prop, "cpu-qe"))
|
|
pdata->qe_mode = 1;
|
|
|
|
ret = of_mpc8xxx_spi_get_chipselects(dev);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = of_address_to_resource(np, 0, &mem);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = of_irq_to_resource(np, 0, &irq);
|
|
if (!ret) {
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
master = mpc8xxx_spi_probe(dev, &mem, irq.start);
|
|
if (IS_ERR(master)) {
|
|
ret = PTR_ERR(master);
|
|
goto err;
|
|
}
|
|
|
|
of_register_spi_devices(master, np);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
of_mpc8xxx_spi_free_chipselects(dev);
|
|
err_clk:
|
|
kfree(pinfo);
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
|
|
{
|
|
int ret;
|
|
|
|
ret = mpc8xxx_spi_remove(&ofdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id of_mpc8xxx_spi_match[] = {
|
|
{ .compatible = "fsl,spi" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
|
|
|
|
static struct of_platform_driver of_mpc8xxx_spi_driver = {
|
|
.name = "mpc8xxx_spi",
|
|
.match_table = of_mpc8xxx_spi_match,
|
|
.probe = of_mpc8xxx_spi_probe,
|
|
.remove = __devexit_p(of_mpc8xxx_spi_remove),
|
|
};
|
|
|
|
#ifdef CONFIG_MPC832x_RDB
|
|
/*
|
|
* XXX XXX XXX
|
|
* This is "legacy" platform driver, was used by the MPC8323E-RDB boards
|
|
* only. The driver should go away soon, since newer MPC8323E-RDB's device
|
|
* tree can work with OpenFirmware driver. But for now we support old trees
|
|
* as well.
|
|
*/
|
|
static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *mem;
|
|
unsigned int irq;
|
|
struct spi_master *master;
|
|
|
|
if (!pdev->dev.platform_data)
|
|
return -EINVAL;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem)
|
|
return -EINVAL;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (!irq)
|
|
return -EINVAL;
|
|
|
|
master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
|
|
if (IS_ERR(master))
|
|
return PTR_ERR(master);
|
|
return 0;
|
|
}
|
|
|
|
static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
|
|
{
|
|
return mpc8xxx_spi_remove(&pdev->dev);
|
|
}
|
|
|
|
MODULE_ALIAS("platform:mpc8xxx_spi");
|
|
static struct platform_driver mpc8xxx_spi_driver = {
|
|
.probe = plat_mpc8xxx_spi_probe,
|
|
.remove = __exit_p(plat_mpc8xxx_spi_remove),
|
|
.driver = {
|
|
.name = "mpc8xxx_spi",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static bool legacy_driver_failed;
|
|
|
|
static void __init legacy_driver_register(void)
|
|
{
|
|
legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
|
|
}
|
|
|
|
static void __exit legacy_driver_unregister(void)
|
|
{
|
|
if (legacy_driver_failed)
|
|
return;
|
|
platform_driver_unregister(&mpc8xxx_spi_driver);
|
|
}
|
|
#else
|
|
static void __init legacy_driver_register(void) {}
|
|
static void __exit legacy_driver_unregister(void) {}
|
|
#endif /* CONFIG_MPC832x_RDB */
|
|
|
|
static int __init mpc8xxx_spi_init(void)
|
|
{
|
|
legacy_driver_register();
|
|
return of_register_platform_driver(&of_mpc8xxx_spi_driver);
|
|
}
|
|
|
|
static void __exit mpc8xxx_spi_exit(void)
|
|
{
|
|
of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
|
|
legacy_driver_unregister();
|
|
}
|
|
|
|
module_init(mpc8xxx_spi_init);
|
|
module_exit(mpc8xxx_spi_exit);
|
|
|
|
MODULE_AUTHOR("Kumar Gala");
|
|
MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
|
|
MODULE_LICENSE("GPL");
|