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92bd868f52
The PCIe PHY version used in SDX65 is v5.20 which has different register offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
15 lines
375 B
C
15 lines
375 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022, Linaro Ltd.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V5_20_H_
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#define QCOM_PHY_QMP_PCS_V5_20_H_
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#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
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#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
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#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
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#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4
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#endif
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