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The CAP3 register contains information about the number of HCHAN (High Capacity) and UCHAN (Ultra High Capacity) channels in UDMAP. Based on this information the start indexes of the levels can be calculated without a need of a table in the match data. On am654 the CAP3 does not contain information about the number different channels. Set up the tpl information based on the available documentation. This change will allow to use the same compatible for different SoCs where the only difference is the number of channel types. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20200717120903.8774-3-peter.ujfalusi@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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*/
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#ifndef K3_UDMA_H_
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#define K3_UDMA_H_
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#include <linux/soc/ti/ti_sci_protocol.h>
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/* Global registers */
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#define UDMA_REV_REG 0x0
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#define UDMA_PERF_CTL_REG 0x4
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#define UDMA_EMU_CTL_REG 0x8
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#define UDMA_PSIL_TO_REG 0x10
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#define UDMA_UTC_CTL_REG 0x1c
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#define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
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#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
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#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
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/* TCHANRT/RCHANRT registers */
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#define UDMA_CHAN_RT_CTL_REG 0x0
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#define UDMA_CHAN_RT_SWTRIG_REG 0x8
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#define UDMA_CHAN_RT_STDATA_REG 0x80
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#define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4))
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#define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \
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UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */
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#define UDMA_CHAN_RT_PEER_STATIC_TR_Z_REG \
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UDMA_CHAN_RT_PEER_REG(1) /* PSI-L: 0x401 */
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#define UDMA_CHAN_RT_PEER_BCNT_REG \
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UDMA_CHAN_RT_PEER_REG(4) /* PSI-L: 0x404 */
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#define UDMA_CHAN_RT_PEER_RT_EN_REG \
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UDMA_CHAN_RT_PEER_REG(8) /* PSI-L: 0x408 */
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#define UDMA_CHAN_RT_PCNT_REG 0x400
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#define UDMA_CHAN_RT_BCNT_REG 0x408
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#define UDMA_CHAN_RT_SBCNT_REG 0x410
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/* UDMA_CAP Registers */
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#define UDMA_CAP2_TCHAN_CNT(val) ((val) & 0x1ff)
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#define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff)
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#define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff)
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#define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff)
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#define UDMA_CAP3_HCHAN_CNT(val) (((val) >> 14) & 0x1ff)
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#define UDMA_CAP3_UCHAN_CNT(val) (((val) >> 23) & 0x1ff)
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/* UDMA_CHAN_RT_CTL_REG */
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#define UDMA_CHAN_RT_CTL_EN BIT(31)
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#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
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#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
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#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
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#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
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/* UDMA_CHAN_RT_PEER_RT_EN_REG */
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#define UDMA_PEER_RT_EN_ENABLE BIT(31)
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#define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
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#define UDMA_PEER_RT_EN_PAUSE BIT(29)
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#define UDMA_PEER_RT_EN_FLUSH BIT(28)
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#define UDMA_PEER_RT_EN_IDLE BIT(1)
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG
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*/
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#define PDMA_STATIC_TR_X_MASK GENMASK(26, 24)
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#define PDMA_STATIC_TR_X_SHIFT (24)
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#define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0)
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#define PDMA_STATIC_TR_Y_SHIFT (0)
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#define PDMA_STATIC_TR_Y(x) \
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(((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK)
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#define PDMA_STATIC_TR_X(x) \
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(((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK)
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#define PDMA_STATIC_TR_XY_ACC32 BIT(30)
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#define PDMA_STATIC_TR_XY_BURST BIT(31)
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG
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*/
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#define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask))
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struct udma_dev;
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struct udma_tchan;
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struct udma_rchan;
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struct udma_rflow;
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enum udma_rm_range {
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RM_RANGE_TCHAN = 0,
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RM_RANGE_RCHAN,
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RM_RANGE_RFLOW,
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RM_RANGE_LAST,
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};
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struct udma_tisci_rm {
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const struct ti_sci_handle *tisci;
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const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
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u32 tisci_dev_id;
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/* tisci information for PSI-L thread pairing/unpairing */
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const struct ti_sci_rm_psil_ops *tisci_psil_ops;
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u32 tisci_navss_dev_id;
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struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
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};
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/* Direct access to UDMA low lever resources for the glue layer */
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int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread);
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int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
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u32 dst_thread);
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struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property);
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void xudma_dev_put(struct udma_dev *ud);
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u32 xudma_dev_get_psil_base(struct udma_dev *ud);
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struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud);
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int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt);
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int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt);
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struct udma_tchan *xudma_tchan_get(struct udma_dev *ud, int id);
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struct udma_rchan *xudma_rchan_get(struct udma_dev *ud, int id);
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struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id);
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void xudma_tchan_put(struct udma_dev *ud, struct udma_tchan *p);
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void xudma_rchan_put(struct udma_dev *ud, struct udma_rchan *p);
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void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p);
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int xudma_tchan_get_id(struct udma_tchan *p);
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int xudma_rchan_get_id(struct udma_rchan *p);
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int xudma_rflow_get_id(struct udma_rflow *p);
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u32 xudma_tchanrt_read(struct udma_tchan *tchan, int reg);
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void xudma_tchanrt_write(struct udma_tchan *tchan, int reg, u32 val);
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u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg);
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void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val);
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bool xudma_rflow_is_gp(struct udma_dev *ud, int id);
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#endif /* K3_UDMA_H_ */
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